A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
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May 20, 2022 - Verilog
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forwarding-unit
Here are 19 public repositories matching this topic...
Verilog Implementation of an ARM LEGv8 CPU
arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit
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Oct 3, 2018 - Verilog
5-Stage Pipelined RISC-V CPU utilizing the RV32I ISA, featuring dynamic branch prediction. Designed, verified, performance tested, and ASIC-flowed
asic gcc verilog systemverilog hazard-detection performance-testing risc-v branch-prediction rv32i gdsii cpu-architecture cocotb forwarding-unit rtl-design riscv-assembly 5-stage-pipeline pipelined-processor directed-testing rtl-verification openlane2
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Sep 13, 2026 - Python
Final Project of the Computer Architecture (ICOM4215) course, Spring 2023. The project documents the journey of three students learning the basics of the vast world of FPGAs and hardware design in general. Here We designed a SPARC-Based Processor in Verilog :D
fpga hardware verilog instruction-semantics computer-architecture forwarding-unit uprm sparcv8 icom-4215 sparc-architecture
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Sep 14, 2023 - Verilog
A pipelined MIPS processor implemented in Verilog, featuring hazard detection and forwarding.
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Sep 13, 2025 - Verilog
A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.
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Jul 22, 2021 - Verilog
ARM processor pipeline implementation. Featuring hazard unit, forwarding unit, SRAM & cache memory.
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Feb 1, 2024 - Verilog
Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coprocessor.
python matrix-multiplication verilog computer-architecture icarus-verilog hardware-acceleration instruction-set-architecture rv32i processor-design forwarding-unit custom-assembler pipelined-processor risk-v risc-v-processor 32-bit-processor gtk-wave verilog-2001 hazard-handling
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Sep 21, 2026 - Verilog
Verilog Implementation of an ARM LEGv8 CPU
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Aug 14, 2018 - Verilog
SystemVerilog RTL implementation of a 5-stage pipelined RISC-V processor with hazard detection, forwarding, stall/flush control, simulation verification, and Vivado synthesis.
fpga simulation verification xilinx synthesis vivado systemverilog computer-architecture hazard-detection risc-v digital-design rv32i waveform-analysis processor-design cpu-design forwarding-unit rtl-design hardware-design pipelined-processor
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May 16, 2026 - SystemVerilog
The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.
mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation
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Oct 27, 2024 - Verilog
Synthesizable 32-bit 5-stage pipelined ARM processor (ARMv4T subset) in Verilog HDL featuring dynamic operand forwarding, load-use hazard detection, and multi-cycle SRAM controller (Zynq-7000 FPGA @ 125 MHz)
fpga verilog vivado pipelining computer-architecture hazard-detection modelsim university-of-tehran arm-processor forwarding-unit
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Sep 23, 2026 - Verilog
32-bit 5-Stage Pipelined Processor designed in Verilog HDL with Forwarding Unit, Hazard Detection, Branch Handling, RTL Verification, and Behavioral Simulation using Xilinx Vivado.
fpga verilog vivado computer-architecture hazard-detection vlsi pipeline-processor digital-design processor-design forwarding-unit
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Jun 24, 2026 - Verilog
Design for a 6-stage pipeline processor that supports load, store, jump, or, beq, bne and andi instructions. Additional support for handling data hazards through stalls, flushing and forwarding.
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Jun 6, 2026 - Verilog
A 32-bit five-stage pipelined RISC processor implemented in Verilog HDL with hazard detection and forwarding.
simulation processor assembly verilog computer-architecture hazard-detection risc digital-design forwarding-unit pipelined-processor
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Jul 21, 2026 - Verilog
Verilog HDL implementation of a 5-stage pipelined RISC-V processor with Hazard Detection and Forwarding Unit verified using EDA playground and EPWave.
verilog computer-architecture hazard-detection pipeline-processor risc-v forwarding-unit eda-playground
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May 25, 2026 - Verilog
ARM processor implementation, hazard unit, forwarding unit, SRAM & cache memory.
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Jul 24, 2023 - Verilog
基于 Verilog 的 16 位 5 级流水线 RISC 处理器，支持数据前推、Load-Use 停顿与跳转冲刷，并在 Xilinx Zynq FPGA 上板验证。
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Aug 27, 2026 - Verilog
RTL implementation of a 32-bit, 5-stage pipelined ARM processor in Verilog, featuring data forwarding, hazard detection, and conditional execution. Verified in ModelSim.
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Sep 2, 2026 - Verilog
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