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1. CORDIC CORDIC Public

   Synthesizable 16-bit, 16-stage pipelined CORDIC engine in Verilog (Q2.14 fixed-point) computing high-throughput sine and cosine without hardware multipliers. Features valid_in/valid_out handshaking…

   Verilog 4

2. rv32i-single-cycle-core rv32i-single-cycle-core Public

   Hardware-synthesizable RV32I single-cycle core in strict Verilog-2001, modeled after Harris & Harris. Implemented on Artix-7 (125 MHz) with dual-port LUTRAM regfile, zero timing violations, and an …

   Verilog 3

3. two-stage-cmos-opamp two-stage-cmos-opamp Public

   Design, simulation(LTspice), and automated Python characterization of a Two-Stage Miller-Compensated CMOS Op-Amp in TSMC 0.18µm. Achieved 71 dB Gain, 52.1 MHz GBW, 63.3° Phase Margin, and 53.7 V/µs…

   Python 3

4. riscv-5stage-pipelined-matmul riscv-5stage-pipelined-matmul Public

   Synthesizable 5-stage pipelined RV32I processor in Verilog featuring full hazard handling (forwarding, load-use stalls, branch flushes) and an integrated 64-cycle 4×4 matrix multiplication coproces…

   Verilog 3

5. over-the-air-digital-modulation-sdr over-the-air-digital-modulation-sdr Public

   "Over-the-air digital communication system using USRP B210: BER analysis and live payload transmission (Audio via BPSK, Text via QPSK) alongside 16-Hexagonal QAM implementation."

   3

6. Boost-Converter Boost-Converter Public

   This repository is about the simulation and working of the DC-DC Boost converter