Apply the allocator gc-gate fix to SD21/SDXL

[TroyHernandez]

Stacked on #24 (needs .flux_gc_gates() from that branch; will retarget
to main when #24 merges).

load_pipeline() now routes through the same allocator gc-gate fix as
the FLUX/Z-Image pipelines whenever any component sits on CUDA. The
legacy SD path had the identical pathology: the torch allocated/reserved
ratio gate is chronically exceeded under backend:native, so R gc fired
on nearly every CUDA allocation.

Measured at 50 steps, warm generation (native modules, decoder on CPU,
RTX 5060 Ti 16 GB):

Model	Before	After	R gc share
SDXL 1024x1024	234 s	100 s	209 s -> 75 s
SD 2.1 768x768	101 s	26 s	88 s -> 15 s

Notes:

• The reduced gc cadence lets the garbage sawtooth ride higher between
  collections (SD21 peak 5.4 -> 13.3 GB alloc on the 16 GB card). The
  gate constants are tuned for 16 GB; smaller cards may need different
  sizing — measurement tracked separately.
• The all-GPU SDXL layout at 1024px peaks ~14 GB with native modules
  and can OOM on 16 GB regardless of gates (decoder was on CPU for
  these measurements). Pre-existing, not changed here.
• README's SDXL/FLUX.2 comparison table numbers were measured under a
  different (undocumented) component layout and are not restated here.

Full suite 692/692.

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