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Apply the allocator gc-gate fix to SD21/SDXL#27

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TroyHernandez merged 13 commits into
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feature/sd-gc-gates
Jul 8, 2026
Merged

Apply the allocator gc-gate fix to SD21/SDXL#27
TroyHernandez merged 13 commits into
mainfrom
feature/sd-gc-gates

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Recreation of #25, which GitHub auto-closed when its stacked base
(feature/zimage, #24) was squash-merged and deleted.

load_pipeline() now routes through the same allocator gc-gate fix as
the FLUX/Z-Image pipelines whenever any component sits on CUDA. The
legacy SD path had the identical pathology: the torch allocated/reserved
ratio gate is chronically exceeded under backend:native, so R gc fired
on nearly every CUDA allocation.

Measured at 50 steps, warm generation (native modules, decoder on CPU,
RTX 5060 Ti 16 GB):

Model Before After R gc share
SDXL 1024x1024 234 s 100 s 209 s -> 75 s
SD 2.1 768x768 101 s 26 s 88 s -> 15 s

Notes:

  • The reduced gc cadence lets the garbage sawtooth ride higher between
    collections (SD21 peak 5.4 -> 13.3 GB alloc on the 16 GB card). The
    gate constants are tuned for 16 GB; smaller cards may need different
    sizing — measurement tracked in Measure the allocator gc-gate fix on an 8 GB card #26.
  • The all-GPU SDXL layout at 1024px peaks ~14 GB with native modules
    and can OOM on 16 GB regardless of gates (decoder was on CPU for
    these measurements). Pre-existing, not changed here.

Full suite 692/692.

🤖 Generated with Claude Code

…R gc

The torch allocated/reserved ratio gate (0.95) is chronically exceeded
under backend:native (measured 0.957 steady state), firing the R gc
callback on nearly every CUDA allocation: ~2,200 gcs x 62 ms per
Z-Image generation. start_torch() reads the gate options only once at
torch init, so the loaders now push thresholds into the live allocator
directly: ratio gate off, absolute allocated_rate 0.65 as the
garbage-accumulation gate, footprint-based reserved_rate as the net.

Measured 1024x1024 on the RTX 5060 Ti 16 GB:
  Z-Image-Turbo 143 -> 24 s, klein 48 -> 13 s, FLUX.1 121 -> 55 s
load_pipeline() now routes through .flux_gc_gates() when any component
is on CUDA. Measured at 50 steps (native modules, decoder on CPU,
RTX 5060 Ti 16 GB), warm generation:

  SDXL 1024x1024: 234 -> 100 s (R gc 209 -> 75 s)
  SD 2.1 768x768: 101 -> 26 s  (R gc 88 -> 15 s)

The reduced gc cadence lets the garbage sawtooth ride higher (SD21
peak 5.4 -> 13.3 GB alloc), so smaller cards may need different gate
sizing.
@TroyHernandez TroyHernandez merged commit 6861d3b into main Jul 8, 2026
0 of 2 checks passed
@TroyHernandez TroyHernandez deleted the feature/sd-gc-gates branch July 8, 2026 20:32
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