Implement STM32F7 SAI1/SAI2 ports with circular DMA

[JaxCalder]

Summary

• Implement STM32F7 SAI1 and SAI2 master I2S/TDM ports with circular DMA. The family-specific port.c supplies only SAI addresses, clock domains and DMA routes; the transfer engine is shared in stm32_common.
• Lease DMA2 streams 1/5, channel 0, for SAI1 TX/RX and streams 4/6, channel 3, for SAI2 TX/RX through published dmdma 0.5. This branch encodes STM32 channel 0 as request 8, which the existing STM32 port maps to CHSEL=0. dmdma PR #5 fixes the core to accept the canonical request 0 for peripheral transfers. Once that change is published, this driver can use 0 directly.
• Use uncached dmheap ping-pong buffers; DMA half/full callbacks move whole PCM frames through bounded TX/RX queues. Keep dmclk_port 1.2 clock ownership and SAI status handling. Existing tests, Makefile and README badges are retained.

Validation

• Built dmsai, dmsai_port, dmsai_port_board_test and the existing test_dmsai target for STM32F7.
• Rebuilt dmod-boot master firmware with local DMFs, deleting modules.dmp and __modules_dmp.o before repackaging. OpenOCD flashed and verified the image. After 30 seconds, UART responded.
• On STM32F746G-DISCO, dmsai_port_board_test reported PASS (0 failures) for SAI1 and SAI2, each at 48 kHz and 44.1 kHz. All four DMA streams advanced; a 300-frame write larger than the TX queue and an RX read completed; transfer errors remained zero. Repeated with locally built dmdma/dmdma_port 0.5.1 from the companion PR, also passing. Separately, a temporary local dmsai build using request 0 passed against the fixed dmdma core.

Device layer

dmdevfs owns node mounting. The architecture-independent dmsai DIF callbacks remain the interface stubs from the earlier PR; the direct SAI port is exercised by the board test. The board test temporarily routes SAI1 pins to AF6 and SAI2 pins to AF10, then restores them. It does not initialize the WM8994 codec or assess analog audio quality.