Openframe GPIO configurator

.cf/openframe_default.json

@@ -0,0 +1,97 @@
+{
+  "schema_version": 1,
+  "gpio": {
+    "unused_mode": "analog",
+    "pads": [
+      {
+        "pad": 0,
+        "mode": "input",
+        "signal": "clk"
+      },
+      {
+        "pad": 1,
+        "mode": "input_pu",
+        "signal": "rst"
+      },
+      {
+        "pad": 2,
+        "mode": "output",
+        "signal": "out",
+        "bit": 0
+      },
+      {
+        "pad": 3,
+        "mode": "output",
+        "signal": "out",
+        "bit": 1
+      },
+      {
+        "pad": 4,
+        "mode": "output",
+        "signal": "out",
+        "bit": 2
+      },
+      {
+        "pad": 5,
+        "mode": "output",
+        "signal": "out",
+        "bit": 3
+      },
+      {
+        "pad": 6,
+        "mode": "output",
+        "signal": "out",
+        "bit": 4
+      },
+      {
+        "pad": 7,
+        "mode": "output",
+        "signal": "out",
+        "bit": 5
+      },
+      {
+        "pad": 8,
+        "mode": "output",
+        "signal": "out",
+        "bit": 6
+      },
+      {
+        "pad": 9,
+        "mode": "output",
+        "signal": "out",
+        "bit": 7
+      },
+      {
+        "pad": 10,
+        "mode": "output",
+        "signal": "out",
+        "bit": 8
+      },
+      {
+        "pad": 11,
+        "mode": "output",
+        "signal": "out",
+        "bit": 9
+      },
+      {
+        "pad": 12,
+        "mode": "output",
+        "signal": "out",
+        "bit": 10
+      }
+    ]
+  },
+  "power": {
+    "domains": [
+      "vccd1"
+    ],
+    "macros": [
+      {
+        "instance": "mprj",
+        "domain": "vccd1",
+        "vdd_pin": "vccd1",
+        "gnd_pin": "vssd1"
+      }
+    ]
+  }
+}

README.md

@@ -106,6 +106,48 @@ This is required for GPIO pad configuration and any other IPM-managed blocks in
 
 ## Development Flow
 
+### Configuring the GPIO pads and power domains
+
+The pad configuration and power domains live in one spec, the `project.openframe` block of
+`.cf/project.json`. `cf init` seeds it from `.cf/openframe_default.json`, which reproduces the example
+timer pinout:
+
+| Pads | Mode | Signal |
+| :--- | :--- | :--- |
+| 0 | input | `clk` |
+| 1 | input with pull-up | `rst` |
+| 2-12 | output | `out[10:0]` |
+| 13-43 | analog (unused) | - |
+
+Power: domain `vccd1`/`vssd1`, feeding macro instance `mprj`.
+
+Edit the spec, then regenerate the derived files:
+
+```bash
+cf gpio-config                  # 44-pad grid: mode, signal/bus bit, pad overrides, power (p)
+cf gpio-config --view           # print the current pinout
+cf openframe generate           # regenerate after editing or importing the spec
+cf openframe generate --check   # fail if the generated files are stale (useful in CI)
+cf openframe export pinout.yaml # standalone YAML/JSON copy, e.g. for review or the web configurator
+cf openframe import pinout.yaml # validate and store a YAML/JSON spec, then regenerate
+```
+
+Generated files (do not edit by hand; they carry a `spec-sha256` of the spec they came from):
+
+- `verilog/rtl/openframe_gpio.v`: one `CF_gpio_config` instance per pad. Its user ports are named after
+  the spec signals (a `bidir` signal `x` becomes `x_in`, `x_out`, `x_oeb`).
+- `openlane/openframe_project_wrapper/power.json`: `VDD_NETS`, `GND_NETS` and `PDN_MACRO_CONNECTIONS`
+  for the wrapper PDN.
+
+> [!NOTE]
+> The current wrapper flow (LibreLane 2.4.x, `config.json`) does not read `power.json` yet; the wrapper
+> still uses the single `vccd1`/`vssd1` domain set in `config.json`. Multi-domain power from the spec
+> arrives with the LibreLane 3.x wrapper PDN.
+
+`verilog/rtl/openframe_project_wrapper.v` instantiates `openframe_gpio` and wires its named ports to your
+macro. When you rename or add signals in the spec, update those connections in the wrapper. Pads in
+`analog` mode have no digital signal; use `analog_io[n]` / `analog_noesd_io[n]` on the wrapper directly.
+
 ### Hardening the Design
 Hardening is the process of synthesizing your RTL and performing Place & Route (P&R) to create a GDSII layout.
 
@@ -118,7 +160,8 @@ cf harden <macro_name>   # Harden a specific macro
 ```
 
 #### Integration
-Instantiate your module(s) in `verilog/rtl/openframe_project_wrapper.v`.
+Instantiate your module(s) in `verilog/rtl/openframe_project_wrapper.v` and connect them to the named
+ports of the generated `openframe_gpio` instance (see above).
 
 Update `openlane/openframe_project_wrapper/config.json` environment variables (`VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS`, `EXTRA_GDS_FILES`) to point to your new macros.
 

ip/dependencies.json

@@ -1,7 +1,7 @@
 {
     "IP": [
         {
-            "CF_gpio_config": "v1.1.4"
+            "CF_gpio_config": "v1.2.0"
         }
     ]
 }

openlane/openframe_project_wrapper/config.json

@@ -4,6 +4,7 @@
     "VERILOG_FILES": [
         "dir::/../../verilog/rtl/openframe_project_netlists.v",
         "dir::/../../verilog/rtl/openframe_project_wrapper.v",
+        "dir::/../../verilog/rtl/openframe_gpio.v",
         "dir::../../ip/CF_gpio_config/rtl/CF_gpio_config.v"
     ],
     "VERILOG_FILES_BLACKBOX": [

openlane/openframe_project_wrapper/power.json

@@ -0,0 +1,13 @@
+{
+    "//": "Generated by `cf openframe generate` from project.openframe.power in .cf/project.json. Do not edit.",
+    "// spec-sha256": "151733931264b0fe1416e572d7fd11d76a4effdec5bf42e1cd0eb14fcdb1db11",
+    "VDD_NETS": [
+        "vccd1"
+    ],
+    "GND_NETS": [
+        "vssd1"
+    ],
+    "PDN_MACRO_CONNECTIONS": [
+        "mprj vccd1 vssd1 vccd1 vssd1"
+    ]
+}

verilog/includes/includes.rtl.caravel_user_project

@@ -1,6 +1,7 @@
 # Caravel user project includes
 -v $(USER_PROJECT_VERILOG)/dv/firmware/spiflash.v
 -v $(USER_PROJECT_VERILOG)/../ip/CF_gpio_config/rtl/CF_gpio_config.v
+-v $(USER_PROJECT_VERILOG)/rtl/openframe_gpio.v
 -v $(USER_PROJECT_VERILOG)/rtl/openframe_project_wrapper.v	     
 -v $(USER_PROJECT_VERILOG)/rtl/picosoc.v
 -v $(USER_PROJECT_VERILOG)/rtl/picorv32.v