new user, running into errors while attempting to follow instructions... #12

I'm following a combination of the instructions at
https://platform.chipfoundry.io/knowledge-base/article/start-a-project
and
https://github.com/chipfoundry/openframe_user_project
on a Fedora 44 VM.

I'm trying to harden the default (timer.v) design, as well as replace it with a SystemVerilog re-implementation (see timer.sv, attached).

I've gone through the following list of steps:

1. git clone https://github.com/chipfoundry/openframe_user_project
2. cd openframe_user_project
3. Optionally (replace with SystemVerilog equivalent implementation):
   a. sed -i "s|rtl/timer.v|rtl/timer.sv|" openlane/user_proj_timer/config.json
   b. sed -i "s|rtl/timer.v|rtl/timer.sv|" signoff/user_proj_timer/openlane-signoff/resolved.json
   c. git mv verilog/rtl/timer.v verilog/rtl/timer.sv
   d. cp ~/timer.sv verilog/rtl/timer.sv
   e. sed -i 's/undef SYNC_RESET/define SYNC_RESET/' verilog/rtl/timer.sv (optionally switch to synchronous reset)
4. python3 -m venv venv; source venv/bin/activate
5. pip install chipfoundry-cli
6. cf init (accept defaults; select "2. Create a new platform project")
7. cf setup
8. chcon -Rt svirt_sandbox_file_t . (on Fedora, allow SELinux docker access to current directory)
9. cf harden --list (returns "openframe_project_wrapper" and "user_proj_timer")
10. cf harden user_proj_timer (succeeds, including LVS!)
11. cf harden openframe_project_wrapper (fails, see below)
12. cf verify --all (fails, see below)
13. cf precheck (fails LVS if using SystemVerilog timer.sv, see Step 3 above, fully succeeds with original timer.v)

I'm running into the following set of issues:

• Step 11 (cf harden openframe_project_wrapper) fails with:

  PermissionError: './openlane/openframe_project_wrapper//../../CF_gpio_config/rtl/CF_gpio_config.v'
  is not located any path readable to LibreLane
  

  Not sure why it insists on looking for CF_gpio_config.v, because if I try to run cf gpio-config after Step 7, I also get:

  GPIO configuration is not available for openframe projects.
  Openframe projects do not use user_defines.v.
  Aborted!
  

• Step 12 (cf verify --all) fails with:

  FileNotFoundError: [Errno 2] No such file or directory: 'user_proj_tests/user_proj_tests.yaml'
  

  Not sure if this is somehow related (or, alternatively, orthogonal) to the previous (Step 11) error...

• Step 13 (cf precheck) -- specifically the "LVS" step: succeeds with the unmodified Verilog design (timer.v), but shows up as failing after I replace the design with a SystemVerilog equivaent (timer.sv, see Optional Step 3 above). Not sure (again) whether this is related to being unable to successfully run cf harden openframe_project_wrapper in Step 11), or something else entirely.

Any clue as to what I might be missing much appreciated!