sigmastar: infinity2m to Ifliegen, NOR and SPI NAND

arch/arm/mach-sigmastar/Kconfig

@@ -24,19 +24,235 @@ config TARGET_MSC316DM
 	  infinity3, QFN, 128 MiB of DDR in the package (the SDK's QFN128M
 	  board).
 
+config TARGET_SSC325
+	bool "SSC325"
+	select SS_INFINITY6
+	help
+	  infinity6. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC325DE
+	bool "SSC325DE"
+	select SS_INFINITY6
+	help
+	  infinity6, as the SSC325. OpenIPC ships it on SPI NAND.
+
+config TARGET_SSC327DE
+	bool "SSC327DE"
+	select SS_INFINITY6
+	help
+	  infinity6, as the SSC325.
+
+config TARGET_SSR621Q
+	bool "SSR621Q"
+	select SS_INFINITY2M
+	help
+	  infinity2m with 256 MiB of DDR, on Xiongmai's NVRs.
+
+config TARGET_SSC375
+	bool "SSC375"
+	select SS_IFADO
+	help
+	  Ifado (SSC032B), QFN88 with 128 MiB of DDR3, in Dahua cameras.
+	  The infinity2m map with infinity6c's FSP-QSPI.
+
+config TARGET_SSC029A
+	bool "SSC029A"
+	select SS_IFORD
+	help
+	  Iford, BGA with 512 MiB of DDR4.
+
+config TARGET_SSC029B
+	bool "SSC029B"
+	select SS_IFORD
+	help
+	  Iford, BGA with 256 MiB of DDR3.
+
+config TARGET_SSC029C
+	bool "SSC029C"
+	select SS_IFORD
+	help
+	  Iford, QFN128 with 128 MiB of DDR3.
+
+config TARGET_SSC034A
+	bool "SSC034A"
+	select SS_IFLIEGEN
+	help
+	  Ifliegen, QFN128 with 128 MiB of DDR3.
+
+config TARGET_SSC034B
+	bool "SSC034B"
+	select SS_IFLIEGEN
+	help
+	  Ifliegen, QFN88 with 64 MiB of DDR3.
+
+config TARGET_SSC333
+	bool "SSC333"
+	select SS_INFINITY6B0
+	help
+	  infinity6b0. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC335
+	bool "SSC335"
+	select SS_INFINITY6B0
+	help
+	  infinity6b0. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC335DE
+	bool "SSC335DE"
+	select SS_INFINITY6B0
+	help
+	  infinity6b0. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC337
+	bool "SSC337"
+	select SS_INFINITY6B0
+	help
+	  infinity6b0. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC337DE
+	bool "SSC337DE"
+	select SS_INFINITY6B0
+	help
+	  infinity6b0. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC30KD
+	bool "SSC30KD"
+	select SS_INFINITY6E
+	help
+	  infinity6e. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC30KQ
+	bool "SSC30KQ"
+	select SS_INFINITY6E
+	help
+	  infinity6e. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC338Q
+	bool "SSC338Q"
+	select SS_INFINITY6E
+	help
+	  infinity6e. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC377
+	bool "SSC377"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC377D
+	bool "SSC377D"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC377DE
+	bool "SSC377DE"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC377QE
+	bool "SSC377QE"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC378DE
+	bool "SSC378DE"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSC378QE
+	bool "SSC378QE"
+	select SS_INFINITY6C
+	help
+	  infinity6c. The IPL sets up the DDR; dram_init() reads its size
+	  from the MIU.
+
+config TARGET_SSD201
+	bool "SSD201"
+	select SS_INFINITY2M
+	help
+	  infinity2m, 64 MiB of DDR in the package.
+
+config TARGET_SSD202D
+	bool "SSD202D"
+	select SS_INFINITY2M
+	help
+	  infinity2m, 128 MiB of DDR in the package.
+
 endchoice
 
 config SS_INFINITY3
 	bool
 
+config SS_INFINITY2M
+	bool
+
+config SS_INFINITY6
+	bool
+
+config SS_INFINITY6B0
+	bool
+
+config SS_INFINITY6E
+	bool
+
+config SS_INFINITY6C
+	bool
+
+config SS_IFORD
+	bool
+
+config SS_IFADO
+	bool
+
+config SS_IFLIEGEN
+	bool
+
+# Iford and Ifliegen: the FSP at 0x100D, BDMA from MIU by channel 1, no MIU
+# write pipe to flush
+config SS_IFORD_FAMILY
+	def_bool SS_IFORD || SS_IFLIEGEN
+
+# What infinity6c, Iford and Ifliegen share: the boot flash's chip select in
+# software, the Ethernet PHY at bank 0x1518 (and, but on Ifliegen, the DDR
+# size in bank 0x1659)
+config SS_I6C_FAMILY
+	def_bool SS_INFINITY6C || SS_IFORD || SS_IFLIEGEN
+
+# The FSP-QSPI whose chip select the boot flash's driver holds in software
+config SS_FSP_SW_CS
+	def_bool SS_I6C_FAMILY || SS_IFADO
+
+# The dies booted with OpenIPC's LX_MEM/mma_heap arguments, whose values
+# depend on the DDR size
+config SS_MMA_BOOTARGS
+	def_bool SS_INFINITY2M || SS_INFINITY6 || SS_INFINITY6B0 || SS_INFINITY6E || SS_I6C_FAMILY || SS_IFADO
+
 config SYS_SOC
 	default "sigmastar"
 
 config SYS_VENDOR
 	default "sigmastar"
 
 config SYS_BOARD
-	default "infinity3"
+	default "ipc"
 
 config SYS_CONFIG_NAME
 	default "sigmastar"

arch/arm/mach-sigmastar/Makefile

@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0+
 
 obj-y += soc.o
+obj-y += lowlevel_init.o

arch/arm/mach-sigmastar/include/mach/sigmastar.h

@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * SigmaStar (MStar) infinity3: MSC313E, MSC316DC, MSC316DM.
+ * SigmaStar (MStar) camera SoCs: infinity3 (MSC313E, MSC316DC, MSC316DM),
+ * infinity2m (SSD201, SSD202D), infinity6 (SSC325), infinity6b0 (SSC333,
+ * SSC335, SSC337), infinity6e (SSC30K, SSC338Q) and infinity6c (SSC377,
+ * SSC378). They share the memory map and most of the register map; what
+ * differs is under the die's name below.
  *
  * Every peripheral sits on the RIU, a bus of 16-bit registers: bank B
  * (256 bytes of register space, 128 registers) at 0x1F000000 + B * 0x200,
@@ -23,20 +27,40 @@
 /* Banks */
 #define SS_BANK_PMSLEEP		0x000E
 #define SS_BANK_PMGPIO		0x000F
-#define SS_BANK_FSP		0x0016
+#define SS_BANK_FSP_PM		0x0016
+#define SS_BANK_FSP_NONPM	0x100D	/* infinity6e, past QFN88 */
 #define SS_BANK_PMTOP		0x001E
 #define SS_BANK_TIMER0		0x0030	/* the PIU timers, timer 0 at reg 0x10 */
-#define SS_BANK_ALBANY0		0x0031	/* the internal Ethernet PHY */
+/* The internal Ethernet PHY */
+#if defined(CONFIG_SS_I6C_FAMILY)
+#define SS_BANK_ALBANY0		0x1518
+#define SS_BANK_ALBANY1		0x1519
+#define SS_BANK_ALBANY2		0x151A
+#elif defined(CONFIG_SS_INFINITY6E)
+#define SS_BANK_ALBANY0		0x1514
+#define SS_BANK_ALBANY1		0x1515
+#define SS_BANK_ALBANY2		0x1516
+#else
+#define SS_BANK_ALBANY0		0x0031
 #define SS_BANK_ALBANY1		0x0032
 #define SS_BANK_ALBANY2		0x0033
+#endif
 #define SS_BANK_BDMA		0x1002	/* channel 0 */
 #define SS_BANK_CHIPTOP		0x101E
+#define SS_BANK_MIU		0x1012
 #define SS_BANK_L3BRIDGE	0x1022
 #define SS_BANK_CLKGEN0		0x1038
 #define SS_BANK_PADTOP		0x103C
 #define SS_BANK_UART0		0x1108
 #define SS_BANK_SCGPCTRL	0x1133
-#define SS_BANK_SDIO0		0x1410	/* the SD host (FCIE5) */
+#define SS_BANK_SCGPCTRL_SD	0x1135	/* Iford: the SD clock's own */
+#define SS_BANK_PADGPIO		0x103E	/* infinity6c */
+/* The SD host (FCIE5) */
+#if defined(CONFIG_SS_INFINITY3) || defined(CONFIG_SS_INFINITY2M)
+#define SS_BANK_SDIO0		0x1410
+#else
+#define SS_BANK_SDIO0		0x1413
+#endif
 #define SS_BANK_EMAC0		0x1510
 #define SS_BANK_EMAC1		0x1511
 
@@ -47,6 +71,21 @@
 #define SS_PM_RESET		SS_REG(SS_BANK_PMSLEEP, 0x2E)
 #define SS_PM_RESET_KEY		0x79
 
+/* infinity6e: the bond, which says which FSP the flash is on */
+#define SS_CHIP_BOND		SS_REG(SS_BANK_CHIPTOP, 0x48)
+#define SS_CHIP_BOND_MASK	0x30
+#define SS_CHIP_BOND_QFN88	0x00
+
+/*
+ * The DDR's size as the IPL left it, log2 of MiB. infinity6c's IPL writes a
+ * fixed 0x6000 to MIU reg 0x69 and the size to bank 0x1659 reg 0x0D.
+ */
+#ifdef CONFIG_SS_I6C_FAMILY
+#define SS_DDR_LOG2_MB		readw(SS_REG(0x1659, 0x0d))
+#else
+#define SS_DDR_LOG2_MB		(readw(SS_REG(SS_BANK_MIU, 0x69)) >> 12)
+#endif
+
 /* PIU timer 0, 32 bits at the 12 MHz crystal rate */
 #define SS_XTAL_HZ		12000000
 #define SS_TIMER0_CTRL		SS_REG(SS_BANK_TIMER0, 0x10)
@@ -60,6 +99,23 @@
 #define SS_UART0_BASE		SS_BANK(SS_BANK_UART0)
 #define SS_UART_HZ		172800000
 
+/*
+ * Ifliegen: the IPL leaves UART0 in the URDMA's DMA mode, its console
+ * bytes going through the TX FIFO at reg 0x17; out of DMA mode UART0 is the
+ * 8250 again. PM sleep reg 9 bit 11 holds its RX off (the SDK's
+ * hal_uart_force_rx_disable() for digmux 0).
+ */
+#define SS_URDMA_CTRL		SS_REG(0x1107, 0x00)
+#define SS_URDMA_DMA_MODE	BIT(1)
+#define SS_URDMA_TX_DMA_EN	BIT(2)
+#define SS_URDMA_RX_DMA_EN	BIT(3)
+#define SS_URDMA_TX_BUSY	BIT(12)
+#define SS_URDMA_RX_BUSY	BIT(13)
+#define SS_URDMA_TXFIFO_STS	SS_REG(0x1107, 0x1C)
+#define SS_URDMA_TXFIFO_EMPTY	BIT(0)
+#define SS_UART0_RX_OFF		SS_REG(SS_BANK_PMSLEEP, 0x09)
+#define SS_UART0_RX_OFF_BIT	BIT(11)
+
 /* L3 bridge: flushes the MIU write pipe, so DMA sees what the CPU wrote */
 #define SS_L3_FLUSH		SS_REG(SS_BANK_L3BRIDGE, 0x05)
 #define SS_L3_FLUSH_STATUS	SS_REG(SS_BANK_L3BRIDGE, 0x10)
@@ -68,8 +124,17 @@
 /* DMA engines take MIU addresses: DDR from 0 */
 #define SS_MIU_ADDR(p)		((unsigned long)(p) - SS_DDR_BASE)
 
+/* ATAGs, where each vendor U-Boot leaves them */
+#ifdef CONFIG_SS_INFINITY3
+#define SS_BOOT_PARAMS		(SS_DDR_BASE + 0x100)
+#else
+#define SS_BOOT_PARAMS		SS_DDR_BASE
+#endif
+
 #ifndef __ASSEMBLY__
 void ss_miu_flush(void);
+unsigned int ss_fsp_bank(void);
+void ss_set_mem_env(void);
 int ms_sdmmc_initialize(void);
 #endif
 

arch/arm/mach-sigmastar/lowlevel_init.S

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * U-Boot is started by the vendor's IPL_CUST, and skips the CP15 setup
+ * (SKIP_LOWLEVEL_INIT). Ifado's IPL_CUST jumps with the MMU and the data
+ * cache still on, its page table at 0x20004000, where the kernel later
+ * builds its own: clean the data cache and turn both off before anything
+ * runs, as cpu_init_cp15 would. Where the MMU is already off this is a
+ * branch.
+ */
+#include <linux/linkage.h>
+
+ENTRY(save_boot_params)
+	mrc	p15, 0, r0, c1, c0, 0		@ SCTLR
+	tst	r0, #(1 << 0)			@ M
+	beq	1f
+	push	{r1-r12, lr}			@ IPL_CUST's stack
+	bl	v7_flush_dcache_all
+	mrc	p15, 0, r0, c1, c0, 0
+	bic	r0, r0, #(1 << 2)		@ C
+	bic	r0, r0, #(1 << 0)		@ M
+	mcr	p15, 0, r0, c1, c0, 0
+	isb
+	mov	r0, #0
+	mcr	p15, 0, r0, c8, c7, 0		@ TLBIALL
+	mcr	p15, 0, r0, c7, c5, 0		@ ICIALLU
+	mcr	p15, 0, r0, c7, c5, 6		@ BPIALL
+	dsb
+	isb
+	pop	{r1-r12, lr}
+1:	b	save_boot_params_ret
+ENDPROC(save_boot_params)