Repository navigation
sigmastar: infinity2m to Ifliegen, NOR and SPI NAND - #107
Merged
Merged
Conversation
Targets for infinity2m (SSD201, SSD202D, SSR621Q), infinity6 (SSC325, SSC325DE, SSC327DE), infinity6b0 (SSC333, SSC335, SSC335DE, SSC337, SSC337DE), infinity6e (SSC30KD, SSC30KQ, SSC338Q), infinity6c (SSC377, SSC377D, SSC377DE, SSC377QE, SSC378DE, SSC378QE), Iford (SSC029A/B/C), Ifado (SSC375) and Ifliegen (SSC034A/B), next to infinity3. Per die: the Ethernet PHY's banks, the FSP the flash is on, the DDR size (the IPL's register, or probed where none is known), the LX_MEM/mma_heap values the vendor images pass, the MIU flush. The board file is now the generic sigmastar/ipc. lowlevel_init.S: save_boot_params cleans the D-cache and turns the MMU off when the loader jumps with it on, as Ifado's IPL_CUST does; the kernel would build its page table over the live one. Ifliegen: UART0 leaves the URDMA's DMA mode before the console (board_early_init_f), and U-Boot keeps to the first 48 MiB, as the SDK's does, since TF-A's SP_MIN stays at 0x23FE0000 as the kernel's PSCI.
The FSP's bank by die (PM or non-PM), the BDMA paths from MIU to the FSP and back, BDMA_PATH2 cleared where the second path register means something else, and on infinity6c, Iford, Ifliegen and Ifado the boot flash's chip select held in software (SS_FSP_SW_CS) for the erase, program and status writes.
The internal PHY's banks and the EMAC RX/TX clocks in SCGPCTRL per die; on Iford and Ifliegen the clock gate open and the MCG gating off, as their mhal_emac.c, and on Iford the MCM control that drops the first frame after an RBQP reset.
The FCIE5 host is the same; its bank, clock select, DDR_MOD timing, pad mux, card power and card detect follow each die's vendor hal_card_platform_<die>.c: infinity2m, infinity6, 6b0, 6e, 6c and Iford.
A raw NAND driver for the SPI NAND that SigmaStar boots from, through the FSP-QSPI: geometry from the SNI the IPL reads (the published images carry a generic one), page and spare by BDMA, the chip select held by QSPI's burst bit, the bad-block table kept in memory like the vendor's. A W25N's buffer mode is turned back on where Iford's IPL leaves it off.
OPENIPC_NAND_KERNEL_VOLUME: OpenIPC's SigmaStar NAND firmware keeps the kernel and a squashfs rootfs in UBI volumes of their own; the helper checks and recovers those. Per die the boot partitions, environment and UBI offsets (infinity2m by its PNI, infinity6c and Iford by their SDKs), and root= by the partition count, since gluebi numbers the volumes after the partitions (mtdblock5, 6 on infinity6c and Iford, 4 on infinity2m). The NOR flash's MTD name is nor0 for the SGS kernels (Iford, Ifliegen, Ifado), NOR_FLASH for the older ones.
build.sh builds 50 images: every die's NOR image and the SPI NAND ones. sigmastar-image.py lays out each die's boot partition around the vendor's first stages (IPL, IPL_CUST, and on Ifliegen TF-A's SP_MIN), carried as binaries in openipc/ with the flash tables (MXP, GCIS, CIS, SNI, PNI) they read: from OpenIPC/u-boot-sigmastar's ipl/, the i2m, Maruko, Iford and Ifliegen SDKs, and for Ifado a Dahua camera's NOR.
PR Summary by QodoAdd SigmaStar infinity2m through Ifliegen NOR and SPI NAND support
AI Description
Diagram
High-Level Assessment
Files changed (64)
|
Code Review by Qodo
1.
|
ms_spinand hands the core a SPI NAND's own ID, Winbond 0xEF or GigaDevice 0xC8, neither in nand_manuf_ids: the manufacturer description is then NULL, and nand_get_flash_type() prints its name. With the default log level that print is compiled out, so qemu's W25N01 and GD5F parts identified; a debug build would fault. Reported by Qodo on #107.
The driver sets its own ECC layout for a 64-byte spare and leaves 128 to the core's default; for any other spare the SNI gives (a 4 KiB part with 256 bytes, say) nand_scan_tail() reaches BUG(). Such a part is now reported and not registered. BDMA_PATH2 stays 0 on every die, as the vendor's SPI NAND driver (drvSPINAND_common_hal.c) writes it, unlike its NOR flash_isp: say so. Reported by Qodo on #107.
ubi_marker_present() read offset 0 of the ubi partition only. If that eraseblock is factory-bad, recovery writes the UBI image past it (nand write skips bad blocks), the marker stays unseen, and every boot goes back to recovery. It now reads the first good eraseblock, where UBI keeps an EC header as on every good one, and takes a corrected read (-EUCLEAN) as data. Reported by Qodo on #107.
…der it ss_set_mem_env() took the 64 MiB row for any size without an exact row: a 512 MiB infinity6c got LX_MEM 64 MiB, as the vendor's board_late_init() does. It now takes the largest row not above the DDR's size (256 MiB there); exact sizes keep their rows. Reported by Qodo on #107.
Iford's hal_card_platform.c sets SC_GP_CTRL (bank 0x1135) reg 0x25 bit 7, taking SDIO0's clock off the 12 MHz boot clock, and CLKGEN 0x43 to bit 7 alone; each clock change then clears the gate and the select and sets bit 6 again. The Iford path set CLKGEN bit 7 only and never the SC_GP_CTRL bit. qemu models neither gate; SD detect, FAT load and raw read-back still pass. Reported by Qodo on #107.
SD0 as Ifliegen's hal_card_platform.c and its board's mmc0 set it up: PADGPIO CLK at 0x0F, CMD and D0-D3 from 0x10, card detect at 0x16 (PAD_PM_SD_CDZ, low with a card in), PADTOP 0x61 SD and CDZ mode, card power from PAD_FUART_RTS (PADGPIO 0x34, low active), the clock as Iford's but with SC_GP_CTRL at bank 0x1133, and the host's MCG off (reg 0x3E bit 14). Ifliegen builds with SD now. qemu ssc034a/ssc034b (mstar-06's SD model): card detect, 4-bit bus, FAT load with the file's CRC, raw write and read-back.
ssc034a-nand and ssc034b-nand. sigmastar-image.py --ifliegen-sni lays out what the SDK's image.mk and spinand.squashfs.tfa.partition.config would: the CIS in each of ten blocks (the SNIB and the part's SNIF, the PNI, the flash list, with snigenerator's boot blocks and CRCs), BOOT at 0x140000 (IPL and IPL_CUST three blocks each, TF-A's SP_MIN, our uImage in a 1 MiB UBOOT) and BOOT_BAK at 0x320000, the environment at 0x500000, UBI from 0x540000. The IPL takes its timeouts from the SNIF, so the CIS carries the flash list's W25N01GV (record 57); the SDK's generic one has none and fails to load. The stages and tables are the SDK's (board/ifliegen/boot/spinand). ms_spinand takes Iford's BDMA path. qemu ssc034a/ssc034b: the chain from NAND, nand erase/write/read against the raw file, env across reset, and mstar-06's SDK 4.9.84 kernel from an OpenIPC UBI (kernel, rootfs, rootfs_data) to a shell, its five partitions listed, root through the ubiblock override.
…y2m NAND runs; memlx past the table
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
U-Boot for every SigmaStar die we have boot stages for, next to infinity3:
ssd201ssd202dssr621qssc325ssc325dessc327dessc333ssc335ssc335dessc337ssc337dessc30kdssc30kqssc338qssc377ssc377dssc377dessc377qessc378dessc378qessc029assc029bssc029cssc029assc375ssc034assc034b./build.shmakes 52 images. The vendor's first stages (IPL, IPL_CUST, and on Ifliegen TF-A's SP_MIN) and the flash tables they read are carried as binaries inopenipc/.New:
ms_spinand(SPI NAND on the FSP-QSPI). Per-die support inms_sflash,ms_emac,ms_sdmmc. An OpenIPC NAND layout with the kernel and a squashfs rootfs in their own UBI volumes. Asave_boot_paramshook for a loader that jumps with the MMU on (Ifado).Not run on silicon. Everything past infinity3 has been tested only under qemu (qemu-hisilicon's per-die machines), and the CI release is the only place the images go: publishing to OpenIPC/firmware is commented out in the companion CI PR. What was checked, per die, is in
CLAUDE.md. The main checks:sfandnanderase, write and read against the raw flash file;login:onssc325de,ssc337de,ssc338qNAND and the NOR dies with published images; the SDK kernels reach a shell or userspace on Iford, Ifado and Ifliegen.Not covered: Mercury6 (no IPL at hand); Iford 029b/029c NAND (only RTOS/dual-OS sets in the SDK).
The CI matrix for these SoCs is in the companion PR against
openipc. Merge this one first: that PR's own run builds the currentopenipc-sigmastar.