Fix SYMRSVDWORD not renaming module names matching C++ keywords

src/V3Name.cpp

@@ -82,6 +82,7 @@ class NameVisitor final : public VNVisitorConst {
         VL_RESTORER(m_modp);
         {
             m_modp = nodep;
+            renameKeywordCheck(nodep);
             iterateChildrenConst(nodep);
         }
     }

test_regress/t/t_mod_rsvd.py

@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Tom and contributors
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["-Wno-SYMRSVDWORD", "-fno-inline"])
+
+test.execute()
+
+test.passes()

test_regress/t/t_mod_rsvd.v

@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Tom and contributors
+// SPDX-License-Identifier: CC0-1.0
+
+// Test that a module with a C++ reserved keyword name is handled correctly
+
+// verilator lint_off SYMRSVDWORD
+
+module register (
+    input wire clk,
+    input wire d,
+    output reg q
+);
+    always @(posedge clk) q <= d;
+endmodule
+
+module t (
+    /*AUTOARG*/
+    // Inputs
+    clk
+);
+
+    input clk;
+
+    reg d;
+    wire q;
+
+    register u_reg (
+        .clk(clk),
+        .d(d),
+        .q(q)
+    );
+
+    integer cyc = 0;
+
+    always @(posedge clk) begin
+        cyc <= cyc + 1;
+        d <= cyc[0];
+        if (cyc == 5) begin
+            $write("*-* All Finished *-*\n");
+            $finish;
+        end
+    end
+
+endmodule