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Fix SYMRSVDWORD not renaming module names matching C++ keywords - #2

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fix-mod-rsvd-keyword
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Fix SYMRSVDWORD not renaming module names matching C++ keywords#2
TJackhammer wants to merge 1 commit into
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fix-mod-rsvd-keyword

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Summary

  • Fixes a bug where a Verilog module named with a C++ reserved keyword (e.g. register) causes a fatal error in the C++ emitter
  • Root cause: V3Name.cpp's visit(AstNodeModule*) did not call renameKeywordCheck(), unlike the visitors for AstVar, AstCFunc, and AstCell
  • Fix: add renameKeywordCheck(nodep) to the AstNodeModule visitor

Test plan

  • Added t_mod_rsvd test with a module named register and -fno-inline to prevent inlining
  • Confirmed test crashes without the fix, passes with it
  • Existing t_var_rsvd, t_var_rsvd_port, and t_var_rsvd_bad tests pass (no regressions)
  • Built and tested with Clang 20.1

Notes

  • Intended for upstream submission to verilator/verilator after internal review
  • AI-assisted development (see Co-Authored-By in commit)

🤖 Generated with Claude Code

The V3Name pass's visit(AstNodeModule*) did not call renameKeywordCheck(),
so module names matching C++ reserved words (e.g. "register") passed
through to the C++ emitter unchanged, causing a fatal error in
V3EmitCSyms::nameCheck().

Add renameKeywordCheck(nodep) to the AstNodeModule visitor, consistent
with how AstVar, AstCFunc, and AstCell are already handled.

Add test t_mod_rsvd to exercise this path with -fno-inline.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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