perf: runtime AVX2 distance dispatch; fix %zu crashes in error paths

[trvon]

Summary

• perf(distances): runtime AVX2+FMA dispatch for float kernels on x86 — portable builds (no SQLITE_VEC_ENABLE_AVX) ran scalar strict-order loops for float inner product, L2 and cosine. New simd/x86_dispatch.hpp adds AVX2+FMA kernels with per-function target attributes (four accumulators) selected after a one-time CPUID check; baseline TUs stay baseline ISA. Compile-time AVX builds and non-GCC/Clang compilers are unchanged; SQLITE_VEC_DISABLE_X86_DISPATCH opts out. Threadripper 3960X, -O2, 20k rows: 384d inner product 268 → 67 ns (4.0x), L2 3.9x, cosine 3.4x; 768d 2.8–4.3x.
• fix(sqlite): format size_t error details with %llu in sqlite3_mprintf — SQLite's printf has no z length modifier; %zu parses as its %z (free-after-use string) conversion, so error paths dereferenced a size_t as char* and crashed. Reachable from invalid input (vec0(embedding float[0])) and from corrupt HNSW persistence (dangling entry point). Six call sites fixed; test_overflow and test_persistence_fuzz now pass instead of segfaulting.
• test(quantization): correct the RaBitQ memory-savings expectation — 384 dims pad to 512 for the FWHT rotation (72 B/vector vs 1536 B FP32 = 21.3x) and 100 vectors carry ~1.7 KB fixed state, so ~17x is correct; the old > 20x (~32x expected) bound failed on every platform.

Tests

• Full suite on Linux x86 (clang, debug, conan sqlite3): 11/11 (previously 3 failures + HNSW timeout at default multiplier). New dispatch-vs-scalar consistency test covers dims 1–70, 384, 768.

AI usage

• AI was used; disclosed here. Prepared with an AI coding assistant; needs maintainer review.

Consumer: trvon/yams perf/simd-release-build. Please merge with a merge commit or rebase (not squash) so the submodule SHA YAMS pins stays reachable, or bump the YAMS pointer after merging.