#
8b10b
Here are 5 public repositories matching this topic...
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Updated
Aug 12, 2024 - SystemVerilog
Implementation of the Aurora 8b/10b Simplex Transmitter
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Feb 15, 2023 - SystemVerilog
Verified USB 3.0 PHY TX datapath in Verilog with PRBS-16 scrambling, 8b/10b encoding, running disparity, and self-checking verification.
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Aug 26, 2026 - Verilog
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