machine/esp32: add ADC driver - #5595
Open
zombieleet wants to merge 1 commit into
Open
Conversation
Implements ADC1 on the Xtensa ESP32: InitADC, Configure and Get for GPIO36, GPIO37, GPIO38, GPIO39, GPIO32, GPIO33, GPIO34 and GPIO35 (channels 0-7). The ADC pins are not contiguous on this chip, so the pin to channel mapping is a lookup rather than arithmetic as on the ESP32-S3. Conversions are driven by the RTC controller under software control, and Get returns the 12-bit sample scaled to 0..65520 to match the other ESP ADC drivers. The analog pads are spread over three unrelated RTC_IO registers (SENSOR_PADS, XTAL_32K_PAD and ADC_PAD), so pad setup is kept local to this file rather than adding a PinAnalog mode to machine_esp32.go. That keeps the change to a single file. Values are raw and uncalibrated. Unlike the ESP32-C3, S3 and C6 drivers there is no eFuse or self-calibration step; accurate voltage mapping should be done with a two-point calibration in user code. ADC2 is not implemented. On the ESP32 it is shared with the Wi-Fi radio and cannot be used reliably while the radio is active. Tested on an ESP32 Coreboard V2 with a photoresistor divider on GPIO36. Readings swept 5056..59824 over the light range, all eight channels returned independent values, and an invalid pin returned an error from Configure and 0 from Get. Signed-off-by: zombieleet <osikwemhev@gmail.com>
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
machine/esp32: add ADC driver
Adds SAR ADC1 support for the original Xtensa ESP32. Until now
machine.ADCexisted as a type on this target but had no
InitADC,ConfigureorGet,so any program using it failed to compile:
What it does
Implements the standard three-symbol ADC contract for
//go:build esp32:All eight ADC1 channels are supported:
Get()returns the 12-bit sample scaled to0..65520(uint16(raw&0xfff) << 4), matching the ESP32-C3, S3 and C6 drivers.Conversions run through the RTC controller under software control:
SAR1_DIG_FORCEselects the RTC controller,MEAS1_START_FORCEandSAR1_EN_PAD_FORCEhand triggering and channel selection to software, thenMEAS1_START_SAR0→1 starts a conversion and the result is read fromMEAS1_DATA_SAR. This mirrors the sequence inmachine_esp32s3_adc.go.Decisions worth reviewing
Single file, no
PinAnalog. The sibling drivers calla.Pin.Configure(PinConfig{Mode: PinAnalog}). On this chip the analog pads arespread across three unrelated
RTC_IOregisters,SENSOR_PADS(GPIO36-39),XTAL_32K_PAD(GPIO32/33) andADC_PAD(GPIO34/35), so routing that throughthe generic pin path would put a large ADC-specific switch into
machine_esp32.go. Pad setup is kept local asconfigureADCPad()instead,keeping this to one new file. Happy to switch to
PinAnalogif preferred.No
ADCnpin constants.board_esp32-coreboard-v2.goalready definesADC0-ADC3, so adding chip-level constants tomachine_esp32.gowouldconflict with it. Also, this chip's ADC pins are non-contiguous, so the
ADC0 = GPIO1style used on the C3/S3 does not transfer cleanly. Left alonepending a naming decision.
Uncalibrated. No eFuse reads and no self-calibration, unlike the C3/S3/C6
drivers. Values are raw; the file documents that accurate voltage mapping needs
a two-point calibration in user code. Calibration can be added later without
changing the API.
ADC2 omitted. It is shared with the Wi-Fi radio on this chip and cannot be
used reliably while the radio is active. The registers are present, so it can
be added later if there is demand.
Testing
Hardware: ESP32 Coreboard V2, photoresistor divider on GPIO36.
Sweeping the light level across its range, 142 samples:
All eight channels read independently, with only GPIO36 connected:
Error paths:
48 conversions across all three pad register groups with no hangs.
Scope of the testing: only GPIO36 (channel 0) had a signal connected. The
other seven channels were confirmed to convert and to return independent
values, so channel selection and pad setup work, but they have not been checked
against a known input. The
XTAL_32K_PADgroup used for GPIO32/GPIO33 is theone I would most like a second pair of eyes on, since those pads are configured
differently from the rest. Happy to test specific channels if a reviewer wants
particular numbers.
Smoke test
Adds
examples/adcforesp32-coreboard-v2to theXTENSAblock ofGNUmakefile, since that board already defines the
ADC2alias the exampleuses: