ISSCC27: Open-source CMOS PTAT temperature sensor with digital calibration

[3more102]

ISSCC 2027 Code-a-Chip submission

This PR adds only:

ISSCC27/submitted_notebooks/ptat_temp_sensor/

Project

Open-Source CMOS PTAT Temperature Sensor with Digital Calibration

The primary artifact is the Jupyter notebook PTAT_Temperature_Sensor_Code_a_Chip.ipynb, with Apache-2.0 licensing, supporting scripts, retained SKY130/open_pdks evidence, and reproducibility checks.

Retained evidence

• Deterministic SKY130 TT/FF/SS dense-grid verification on a 5 °C grid.
• Fixed five-point PWL release calibration at −40, −20, 0, 50, 125 °C.
• Worst retained deterministic dense-grid PWL error: about 0.472 °C.
• Behavioral/external 12-bit, 1.8 V ADC model with gain 10.
• Retained 100-seed SKY130 tt_mm local-mismatch evidence.
• Disjoint-seed low-power and sizing-candidate validation.

The retained baseline 100-seed local-mismatch result does not meet the internal statistical targets:

• temperature-error yield: 66% at ≤0.5 °C;
• branch-mismatch yield: 4% at ≤1%.

Independent sizing-candidate validation also remains a negative engineering result. Candidate i1_m16_s1 passes deterministic dense TT/FF/SS verification and the behavioral readout budget, but on the disjoint 100-seed validation set achieves:

• temperature-error yield: 66%;
• branch-mismatch yield: 64%.

Its final machine-evaluated status is NOT_QUALIFIED_FOR_RELEASE_REVIEW, so the release architecture remains unchanged.

Evidence boundaries

• No silicon measurements are claimed.
• No DRC/LVS/PEX PASS is claimed.
• No transistor-level ADC implementation is claimed.
• No whole-chip power claim is made.
• Exploratory calibration or sizing results are not promoted beyond their retained evidence class.

The contribution is an evidence-driven, reproducible open-source design-closure workflow for a CMOS PTAT sensor rather than a claim of a new PTAT device topology.