Pinned Loading

1. cocotb_video_source cocotb_video_source Public

   Simulation models for camera video source in Cocotb

2. itu_bt_656_to_axis itu_bt_656_to_axis Public

   Synthesizeable core for conversion of ITU-R BT.656 to AXI Stream

   SystemVerilog

3. PeakRDL-regblock PeakRDL-regblock Public

   Forked from SystemRDL/PeakRDL-regblock

   Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

   Python

4. peakView peakView Public

   A TUI for interacting with FPGA CSRs written in the SystemRDL format through an FTDI module

   Rust

5. spi-to-axi-bridge spi-to-axi-bridge Public

   Forked from airhdl/spi-to-axi-bridge

   An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller. Fully compatible with Verilator simulation and yosys synthesizer.

   VHDL

6. HLS-FIR-Accelerator HLS-FIR-Accelerator Public

   A FIR hardware accelerator extension to Berkley's Rocketchip project

   C++