Rustc pull update

crates/core_arch/src/amdgpu/mod.rs

@@ -351,13 +351,13 @@ pub unsafe fn sched_barrier<const MASK: u32>() {
 /// Combining multiple `sched_group_barrier` intrinsics enables an ordering of specific instruction types during instruction scheduling.
 /// For example, the following enforces a sequence of 1 VMEM read, followed by 1 VALU instruction, followed by 5 MFMA instructions.
 ///
-/// ```rust
+/// ```ignore (only available on AMD)
 /// // 1 VMEM read
-/// sched_group_barrier::<32, 1, 0>()
+/// sched_group_barrier::<32, 1, 0>();
 /// // 1 VALU
-/// sched_group_barrier::<2, 1, 0>()
+/// sched_group_barrier::<2, 1, 0>();
 /// // 5 MFMA
-/// sched_group_barrier::<8, 5, 0>()
+/// sched_group_barrier::<8, 5, 0>();
 /// ```
 ///
 #[doc = include_str!("intrinsic_is_convergent.md")]

crates/core_arch/src/nvptx/mod.rs

@@ -157,10 +157,13 @@ unsafe extern "C" {
     /// * `format`: A pointer to the format specifier input (uses common `printf` format).
     /// * `valist`: A pointer to the valist input.
     ///
-    /// ```
+    /// ```ignore (available only for nvptx)
+    /// # use std::mem::transmute;
     /// #[repr(C)]
     /// struct PrintArgs(f32, f32, f32, i32);
     ///
+    /// let a = 0.1f32;
+    /// let b = 0.2f32;
     /// vprintf(
     ///     "int(%f + %f) = int(%f) = %d\n".as_ptr(),
     ///     transmute(&PrintArgs(a, b, a + b, (a + b) as i32)),

crates/core_arch/src/x86/mod.rs

@@ -39,7 +39,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]
@@ -82,7 +86,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]
@@ -125,7 +133,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]
@@ -172,7 +184,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]
@@ -215,7 +231,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]
@@ -258,7 +278,11 @@ types! {
     ///
     /// # Examples
     ///
-    /// ```
+    #[cfg_attr(any(target_arch = "x86", target_arch = "x86_64"), doc = "```")]
+    #[cfg_attr(
+        not(any(target_arch = "x86", target_arch = "x86_64")),
+        doc = "```ignore (only works on x86 targets)",
+    )]
     /// #[cfg(target_arch = "x86")]
     /// use std::arch::x86::*;
     /// #[cfg(target_arch = "x86_64")]

rust-version

@@ -1 +1 @@
-fcbe7917ba18120d9eda136f1c7c5a60c78e554e
+f73951df0a5566d94d13b7954acd9f4ab1fa3734