Origin tracking through standard-cell mapping (&nf)#13
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Follow-on to PR berkeley-abc#487. Documents the verified gap (the &nf standard-cell mapper is not vOrigins-instrumented, and LibreLane's classic abc/BLIF channel loses AIG object identity), and scopes the minimal ABC change: instrument &nf via a Gia_ManOriginsDupNf helper mirroring Gia_ManOriginsDupIf, reusing the existing "y"-extension emission. Co-developed-by: Claude Code v2.1.195 (claude-opus-4-8)
Incorporate authoritative direction from Alan Mishchenko / Dan Ravenslofty and the PR threads: - Record Alan's endorsement of lightweight vOrigins and his explicit engine list (which names &nf); add a verified engine-coverage table showing &nf is the sole remaining uninstrumented engine. - Record the acceptance criterion: zero change to default behavior. - Mark the Nr_Man_t retention-manager lineage (YosysHQ/abc#41, Silimate#4, incl. its classic-abc/write_blif path) as REJECTED by Alan; do not revive. - Note upstream-home reality: yosys consumer (YosysHQ/yosys#5712) closed -> fork-only; "abc9 everywhere" ruled out (YosysHQ/yosys#5679 removed abc9 -liberty). abc side has a home via berkeley-abc#487. Co-developed-by: Claude Code v2.1.195 (claude-opus-4-8)
Spike + empirical check (standalone abc, PR berkeley-abc#487 binary, sky130 liberty, on a yosys XAIGER carrying the "y" extension) show &nf maps in place (Nf_ManDeriveMapping returns p->pGia, no renumber) and the surrounding dups (DupMuxes/DupUnnormalize/DupNormalize) already propagate origins. Origins are preserved across &nf (13 -> 13). So no giaNf.c change / no Gia_ManOriginsDupNf is needed; the deliverable is a regression test only. Rewrites the ABC-PR scope from "instrument &nf" to "verify-only", records the spike evidence, and notes the inconclusive (unfaithful) file round-trip belongs to the yosys consumption work. Co-developed-by: Claude Code v2.1.195 (claude-opus-4-8)
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Superseded: the &nf work is verify-only (origins preserved by construction) and the regression test folds into berkeley-abc#487. Design doc moved to the integration working dir. Closing this stacked PR. |
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Follow-on to berkeley-abc#487 (per-object origin tracking,
vOrigins), extending\srcprovenance from the FPGA/LUT path to standard-cell mapping so ASIC flows
(LibreLane → sky130/gf180) can label mapped gates with RTL source locations.
This PR currently contains the design plan (
STDCELL_ORIGIN_TRACKING_PLAN.md);implementation lands on top.
Verified gap
&nf(std-cell mapper,giaNf.c) is notvOrigins-instrumented (PR Add per-object origin tracking (vOrigins) to Gia_Man_t berkeley-abc/abc#487only covered
&if/&jf/&lf+ opt passes).&writealready emitsvOriginsas the"y"extension — so an instrumentedmapped GIA emits for free.
abcpass round-trips over BLIF, which discards AIGobject identity (the key the
"y"extension relies on) — so end-to-endconsumption needs a yosys-side XAIGER std-cell channel (documented, out of
scope here).
Minimal ABC scope
&nfingiaNf.cto propagate origins to the mapped GIA.Gia_ManOriginsDupNfingiaDup.c(mirror ofGia_ManOriginsDupIf),prototype in
gia.h.&write"y"emission for mapped GIAs.&get; &st; &dch; &nf -L <genlib>; &write -y→assert origins on mapped nodes via
&origins.See
STDCELL_ORIGIN_TRACKING_PLAN.mdfor full detail, risks, and the companionyosys plan.
🤖 Draft created with Claude Code