FROMLIST: pinctrl: qcom: lpass-lpi: PM clock framework cleanup and fixes#464
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RaviHothi wants to merge 3 commits intoqualcomm-linux:qcom-6.18.yfrom
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FROMLIST: pinctrl: qcom: lpass-lpi: PM clock framework cleanup and fixes#464RaviHothi wants to merge 3 commits intoqualcomm-linux:qcom-6.18.yfrom
RaviHothi wants to merge 3 commits intoqualcomm-linux:qcom-6.18.yfrom
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April 14, 2026 16:39
…runtime PM Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Link: https://lore.kernel.org/all/20260413122233.375945-2-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
…eturn types The LPI GPIO register access helpers previously returned the value from ioread32(), even though their return type was int. This mixes data return with status and is inconsistent with common kernel helper conventions. Rework lpi_gpio_read() and lpi_gpio_write() to return an int status and use output parameters to pass register values. Update all callers to match the new helper interface. This change fixes the helper API and resulting call sites without intending any functional change in GPIO or pinctrl behavior. Link: https://lore.kernel.org/all/20260413122233.375945-3-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
Ensure the LPI pinctrl device clocks are runtime resumed before accessing GPIO registers and autosuspended after the access completes. Guard GPIO register read and write helpers with synchronous runtime PM calls so the device is active during MMIO operations. Link: https://lore.kernel.org/all/20260413122233.375945-4-ajay.nandam@oss.qualcomm.com/ Signed-off-by: Ajay Kumar Nandam <ajay.nandam@oss.qualcomm.com>
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This series updates the Qualcomm LPASS LPI pinctrl driver to use the
generic PM clock framework and fixes clock handling around GPIO register
access.
The changes ensure clocks are resumed before register access and
properly suspended afterward, avoiding unsafe register reads when the
device is runtime suspended.
CRs-Fixed: 4400613