PENDING: arm64: dts: qcom: monaco-evk: add overlay for QPS615 ethernet

Add an overlay devicetree for Monaco EVK for temporary enablement of the
QPS615 PCIE switch's 10GbE and 2.5Gbe ethernet ports.

Signed-off-by: Mohd Ayaan Anwar <mohd.anwar@oss.qualcomm.com>

Author: ayaan-anwar

arch/arm64/boot/dts/qcom/Makefile

@@ -429,6 +429,8 @@ monaco-camx-el2-dtbs	:= monaco-evk-el2.dtb monaco-evk-camx.dtbo monaco-camx-el2.
 
 dtb-$(CONFIG_ARCH_QCOM)	+= monaco-camx-el2.dtb
 
+dtb-$(CONFIG_ARCH_QCOM)	+= monaco-evk-staging.dtbo
+
 qcs615-ride-camx-dtbs	:= qcs615-ride.dtb qcs615-ride-camx.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride-camx.dtb

arch/arm64/boot/dts/qcom/monaco-evk-staging.dtso

@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&eeprom1 {
+	nvmem-layout {
+		mac_addr1: mac-addr@0 {
+			reg = <0x0 0x6>;
+		};
+
+		mac_addr2: mac-addr@6 {
+			reg = <0x6 0x6>;
+		};
+	};
+};
+
+&pcieport0 {
+	pcie@0,0 {
+		pcie@3,0 {
+			pci@0,0 {
+				interrupts-extended = <&tlmm 40 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				nvmem-cells = <&mac_addr1>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&aqr_intn_wol_sig>;
+				phy-reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+				reset-deassert-us = <221000>;
+			};
+
+			pci@0,1 {
+				interrupts-extended = <&tlmm 39 IRQ_TYPE_EDGE_FALLING>;
+				interrupt-names = "wol_irq";
+				nvmem-cells = <&mac_addr2>;
+				nvmem-cell-names = "mac-address";
+				pinctrl-names = "default";
+				pinctrl-0 = <&napa_intn_wol_sig>;
+				phy-reset-gpios = <&expander5 0 GPIO_ACTIVE_HIGH>;
+				reset-deassert-us = <20000>;
+			};
+		};
+	};
+};
+
+&tlmm {
+	qps615_intn_wol {
+		aqr_intn_wol_sig: aqr-intn-wol-sig {
+			pins = "gpio40";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+
+		napa_intn_wol_sig: napa-intn-wol-sig {
+			pins = "gpio39";
+			function = "gpio";
+			input-enable;
+			bias-disable;
+		};
+	};
+};