feat: rvr extention for rv64 riscv by mansur20478 · Pull Request #2876 · openvm-org/openvm

mansur20478 · 2026-06-11T14:09:15Z

RVR extension for RV64 RISCV. The current implementation was tested on openvm-riscv-integration-tests tests.

The RVR extension required following changes on top of rvr-rv32:

Adding new W ALU and Mult/Div instructions, new lwu instruction.
Updating lifter to lift new instructions.
Updating instruction simulation done in block generation phase to 64bit.
Updating C code emission to emit 64bit instructions (MULH instruction uses __int128 to avoid overflow of 64bit multiplication to get upper 64bit of the result). Adding 64bit and 32bit sign extended reads in rvr.
Updating RvState registers to 64bit.
Updating bridge.rs - the buffer access between VmState and rvr:ffi, to 64bit.

towards INT-8107

github-actions · 2026-06-11T19:50:41Z

Code review

No issues found. Checked for bugs and CLAUDE.md compliance.

shuklaayush

some comments - primarily pc should become u64 even if at the moment we don't support pc above 30 bits

github-actions · 2026-06-12T18:47:26Z

group	app.proof_time_ms	app.cycles	leaf.proof_time_ms
fibonacci	1,659	4,000,051	529
keccak	16,105	14,365,133	3,002
sha2_bench	10,428	11,167,961	1,948
regex	1,528	4,090,656	424
ecrecover	481	112,210	305
pairing	617	592,827	290
kitchen_sink	3,972	1,979,971	871

Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights.

Commit: 125023d

Benchmark Workflow

gdmlcjs

Same comment changes ("RV32" -> "RV64") in

crates/vm/src/arch/rvr/debug.rs:58
crates/vm/src/arch/rvr/execute.rs:97

gdmlcjs · 2026-06-12T22:52:24Z

    }
 }

 /// HINT_RANDOM phantom: fill the hint stream with `reg[num_words_reg] * 4`


I think the 4 should be changed to 8

shuklaayush

some comments but we can address in a follow up

shuklaayush · 2026-06-14T08:00:25Z

+                                assert!(
+                                    t < (1u64 << PC_BITS),
+                                    "JumpDyn target {t:#x} exceeds PC address space"
+                                );
+                                let pc32 = t as u32;


let's try to avoid converting pc to u32 altogether if possible. also better to emit errors instead of panicing

shuklaayush · 2026-06-14T08:01:00Z

@@ -79,10 +79,10 @@ pub fn init_rvr_state<F: PrimeField32>(
    vm_state: &mut VmState<F, GuestMemory>,
    pc: u32,


we should change it to u64

shuklaayush · 2026-06-14T08:02:44Z

+            vm_state.set_pc(
+                u32::try_from(state.pc).expect("PC must be within u32 range after C bounds check"),
+            );


not the most ideal, we should change pc to u64 but check that it's within PC_BITS

RVR extension for RV64 RISCV. The current implementation was tested on `openvm-riscv-integration-tests` tests. The RVR extension required following changes on top of `rvr-rv32`: 1) Adding new `W` ALU and Mult/Div instructions, new `lwu` instruction. 2) Updating lifter to lift new instructions. 3) Updating instruction simulation done in block generation phase to 64bit. 4) Updating `C` code emission to emit 64bit instructions (`MULH` instruction uses `__int128` to avoid overflow of `64bit` multiplication to get upper 64bit of the result). Adding 64bit and 32bit sign extended reads in rvr. 5) Updating `RvState` registers to 64bit. 6) Updating `bridge.rs` - the buffer access between `VmState` and `rvr:ffi`, to 64bit. towards INT-8107

feat: rvr extention for rv64 riscv

e4a4ec4