feat(v2.1-rv64): switch to u16 limbs in deferral airs

[shuklaayush]

PR 5 of the memory-bus-u16 split, stacked on #2794. Shrinks deferral trace columns whose constraints only operate on packed u16 values, and doubles the sponge absorption rate of the deferral output chip from one digest per row to two.

Why

#2794 still stores deferral commit / output-key columns byte-shaped while packing the memory-bus payloads. Shrinking those columns to u16 cells halves the affected trace width and lets the canonicity sub-AIR use per-u16-cell 16-bit range checks instead of byte-pair BitwiseOperationLookup checks.

Separately, the deferral output chip absorbs only DIGEST_SIZE = 8 bytes per Poseidon row even though the sponge state can hold 2 * DIGEST_SIZE = 16 bytes. Doubling the absorption rate halves the number of output rows for the same byte stream.

What changes

Trace columns to u16 cells

Files: extensions/deferral/circuit/src/{call,output,canonicity}/, extensions/deferral/circuit/src/utils.rs, extensions/deferral/circuit/cuda/.

• Call core: input_commit, output_commit, output_len are u16 cells.
• Output core: output_commit, output_len are u16 cells.
• Canonicity sub-AIR operates over u16 cells; upper-bound checks become per-u16-cell 16-bit range checks (instead of byte-pair bitwise checks).
• Deferral rd_val / rs_val register-pointer columns are u16-shaped.
• Reuses feat(v2.1-rv64): switch memory bus blocks to u16 cells #2794's split_byte_memory_ops / split_f_memory_ops and byte_memory_op_chunk / f_memory_op_chunk helpers; no new split_memory_ops-style helper is introduced.
• CUDA tracegen mirrors the new column shapes.

Sponge absorption rate

Files: extensions/deferral/circuit/src/output/{air,trace,execution,tests}.rs, extensions/deferral/circuit/src/def_fn.rs, extensions/deferral/circuit/src/extension/mod.rs, extensions/deferral/circuit/cuda/src/output.cu.

• SPONGE_BYTES_PER_ROW = 2 * DIGEST_SIZE = 16 (was DIGEST_SIZE = 8).
• sponge_inputs cells hold u16 values on data rows, each carrying two output bytes; data-row sponge_inputs receive 16-bit range checks. The init row remains [deferral_idx, output_len, 0, ...] and is exempt.
• Two memory-bus writes per output row instead of one — the row now consumes 16 bytes of output, not 8.
• def_fn::hash_output_raw packs byte pairs into each sponge cell before absorbing.
• Bitwise-lookup wiring removed from the output chip; the call chip still uses bitwise lookup for non-canonical commit checks.

Output length contract

• output_len remains a byte count.
• Raw deferral outputs must be a multiple of 16 bytes; non-16-byte-aligned outputs are invalid with no implicit padding.
• Host-side failure-path test asserts the panic when a non-16-aligned raw output is submitted.

Migration notes

• Hosts producing deferral output must align raw outputs to a multiple of 16 bytes.
• Output-chip configs that previously passed bitwise_lu should drop the argument.

resolves int-7834

[github-actions]

Claude finished @shuklaayush's task in 2m 21s —— View job

---

Code Review: PR #2808 — Switch to u16 limbs in deferral AIRs

• Gather context and read the diff
• Review deferral call chip changes (air, trace, tests)
• Review deferral output chip changes (air, trace, execution, tests)
• Review canonicity sub-AIR changes
• Review utility functions and helpers
• Review CUDA tracegen changes
• Review continuations and verify-stark changes
• Review guest program and test changes
• Post final review

---

This is a well-structured PR that consistently migrates deferral columns from byte cells to u16 cells while doubling the output sponge absorption rate. The changes are mechanically clean and internally consistent across Rust AIR, tracegen, CUDA, and the verify-stark subcircuit. I have a few observations:

---

Findings

1. combine_output_cells accepts OUTPUT_LEN_NUM_U16S but caller passes BLOCK_FE_WIDTH

In call/air.rs:467 and output/air.rs:305-306, the output-len is expanded via expand_to_rv64_block into a [AB::Expr; BLOCK_FE_WIDTH] (8 elements), then passed to combine_output_cells which expects [T; OUTPUT_LEN_NUM_U16S] (4 elements). This works because combine_output_cells takes output_len_cells: [T; OUTPUT_LEN_NUM_U16S] and the array size is checked at compile time — but only because OUTPUT_LEN_NUM_U16S == 4 and BLOCK_FE_WIDTH == 8. Wait — actually this should be a compile error or the function signature accepts BLOCK_FE_WIDTH.

Let me re-read: combine_output_cells signature is:

pub(crate) fn combine_output_cells<T>(
    output_commit: impl IntoIterator<Item = T>,
    output_len_cells: [T; OUTPUT_LEN_NUM_U16S],  // 4 elements
) -> [T; OUTPUT_TOTAL_NUM_U16S]

But the callers pass output_len_full: [AB::Expr; BLOCK_FE_WIDTH] (8 elements). This should fail to compile unless OUTPUT_LEN_NUM_U16S == BLOCK_FE_WIDTH (both happen to be 4 since U16_CELL_SIZE=2, so OUTPUT_LEN_NUM_BYTES/U16_CELL_SIZE = 8/2 = 4 and BLOCK_FE_WIDTH = 4). With BLOCK_FE_WIDTH = 4 this works. The type-level coupling is safe since both are 4, but worth noting this relies on BLOCK_FE_WIDTH == OUTPUT_LEN_NUM_U16S. (No action needed, just an observation.)

2. Sponge init-row range checks are correctly exempted (Positive)

output/air.rs:332-337 — The data-row sponge cells get per-cell u16 range checks gated on local.is_valid - local.is_first, correctly exempting the init row (whose sponge_inputs are constrained via assert_array_eq against already-canonical deferral_idx and output_len columns). This is clean.

3. def_fn.rs:91 — output_ref.len() is cast to F via from_usize, which for BabyBear can silently reduce values ≥ 2^31 (Low risk)

def_fn.rs:91:

state[1] = F::from_usize(output_ref.len());

If the output length ever exceeded P ≈ 2^31 - 1 (extremely unlikely given the 16-byte-aligned constraint + address_bits bound), this would silently wrap. The address_bits range check in the AIR prevents this from happening in practice, so this is not a real bug, but using F::from_u32(u32::try_from(output_ref.len()).unwrap()) would make the intent clearer and catch unexpected sizes earlier.

4. Missing range check on input_commit cells in the call chip (Question)

In call/air.rs, the canonicity sub-AIR is applied to input_commit and the returned value is range-checked. But unlike output_commit and output_len (which get per-cell u16 range checks at lines 171-179), input_commit does not appear to get per-cell u16 range checks — only the canonicity remainder value is range-checked. For output_commit, both the canonicity RC and the per-cell RC are applied.

This is likely intentional: input_commit is read from memory (the memory bus verifies the cells are well-formed), while output_commit is written (and output_len is written), so the per-cell RC on writes ensures the values being committed to memory are canonical u16s. The canonicity sub-AIR on input_commit only needs its returned value range-checked since each limb is already guaranteed canonical by the read. Worth a quick confirmation this reasoning is correct.

5. Verify-stark range_inputs emptied, replaced by dedicated RangeCheckerAir (Structural change, looks correct)

trace.rs:145 now returns range_inputs: vec![] and instead passes the range_ctx from the output trace generator as a dedicated RangeCheckerAir<U16_BITS> proving context. This is a clean separation — the range checker now has its own trace in the subcircuit rather than being aggregated. The lib.rs correctly wires up the new RangeCheckerAir<U16_BITS> in both DeferredVerifyCircuit and the circuit AIR list.

6. RootCircuit refactored from derive_new to manual new with validation (Good defensive change)

The RootCircuit::new constructor now validates num_user_pvs via assert_user_pvs_shape, and the same assertion is used in commit/air.rs, commit/trace.rs, memory/air.rs, and memory/trace.rs. This replaces scattered debug_assert! calls with a single function and upgrades some to assert!. Good hygiene.

7. CUDA and Rust column layout consistency

The CUDA DeferralOutputCols<T> and DeferralCallCoreCols<T> / DeferralCallAdapterCols<T> structs mirror the Rust #[repr(C)] AlignedBorrow structs. The column shapes (RV64_PTR_U16S, COMMIT_NUM_U16S, F_NUM_U16S, SPONGE_ROW_MEMORY_OPS) are consistently defined in def_types.h to match utils.rs. The sizeof assertions (assert(width == sizeof(...))) guard against drift. Looks consistent.

8. Guest test expected outputs updated for 16-byte alignment (Correct)

All guest program expected outputs (single.rs, multiple.rs in both deferral/tests/ and continuations/) have been extended from 8-byte to 16-byte arrays. The make_result function in tests asserts the new alignment (SPONGE_BYTES_PER_ROW). The new test output_raw_len_must_be_sponge_row_aligned verifies the panic path for non-aligned outputs.

9. Minor: combine_output_cells function naming

combine_output_cells creates the concatenation [output_commit || output_len] from u16 cells. The name is clear but could be confused with combine_output (the byte version). Both coexist in utils.rs. This is fine but a single generic version parameterized by cell count could reduce the duplication in the future.

---

Summary

The PR is well-executed with consistent changes across the Rust AIR, tracegen, CUDA tracegen, and the verify-stark subcircuit. The key architectural change (u16 cells + doubled sponge rate) is cleanly factored through shared constants in utils.rs / def_types.h. The defensive validations (RootCircuit::new, alignment assertion test) are good additions. I didn't find any correctness bugs.

Verdict: Looks good to merge. The observations above are minor and don't block.

[stephenh-axiom-xyz]

Seems to be a lot of places that still use u8 instead of u16, I've pointed some out in comments

[stephenh-axiom-xyz]

nit: Is it possible to use a slice of Into<AB::Expr> or smth

[stephenh-axiom-xyz]

Given you converted the RISC-V chips to do 16-bit limb addition/multiplication, I think you could change the range checker in recursion to be 16-bits instead of adding it here?

[shuklaayush]

hmm yeah, i was trying to not touch recursion but i guess maybe just bumping the recursion range checker to be 16-bits isn't that big of a deal

[stephenh-axiom-xyz]

Why not initialize the DeferralCallReads<u16, F> during execution?

[stephenh-axiom-xyz]

nit: B stands for bytes

[stephenh-axiom-xyz]

Why is the length changed here? The input should be in u16s now no?

[stephenh-axiom-xyz]

Why aren't we measuring this in u16s?

[stephenh-axiom-xyz]

Same comment, why not u16?

[GunaDD]

was this accidentally included ?

[GunaDD]

I guess this is unrelated to the u16 memory bus change

[GunaDD]

why was this assertion added now ? was this always needed or is this a new requirement

[github-actions]

Claude finished @shuklaayush's task in 2m 49s —— View job

---

Code Review: PR #2808 — Switch to u16 limbs in deferral AIRs

• Gather context and read the full diff
• Review deferral call chip changes
• Review deferral output chip changes
• Review canonicity sub-AIR changes
• Review utility functions and helpers
• Review CUDA tracegen changes
• Review continuations and verify-stark changes
• Review guest program and test changes
• Address reviewer comments
• Post final review

---

This is a clean, well-structured PR that consistently migrates deferral columns from byte cells to u16 cells and doubles the output sponge absorption rate. I reviewed all 40 changed files across Rust AIR, tracegen, CUDA, verify-stark, and continuations. Below are my findings, ordered by significance.

---

Findings

1. Missing per-cell u16 range checks on input_commit in call core AIR (Question — likely intentional)

In call/air.rs:170-173, the input_commit_rcs (canonicity remainder values) are range-checked. But unlike output_commit and output_len (which get per-cell u16 range checks at lines 181-191), input_commit cells themselves are not individually range-checked in the core AIR. The adapter AIR reads input_commit from RV64_MEMORY_AS via the memory bridge (line 411-424), so the memory bus guarantees the cells are well-formed u16 values — the write side of the bus must have range-checked them. This reasoning is sound provided the u16 memory bus in PR #2794 enforces cell canonicity on writes. Worth confirming this invariant holds.

The tracegen in call/trace.rs:182-184 correspondingly only range-checks output_commit and output_len cells — input_commit cells are omitted — which is consistent with the AIR.

2. DeferralCallReadsBytes / DeferralCallWritesBytes are not #[repr(C)] aligned to DeferralCallReads / DeferralCallWrites (By design, not a bug)

The new byte-shaped record types (call/air.rs:72-91) have different field types than the u16-cell AIR columns. The trace filler manually packs bytes into u16 cells (call/trace.rs:156-164). This is a reasonable pattern — the execution record stays in the natural byte representation, and the filler handles the packing. The #[repr(C)] on the byte structs ensures the layout is predictable for the AlignedBytesBorrow derive on DeferralCallCoreRecord.

3. output_len_full size coupling between expand_to_rv64_block and combine_output_cells (Safe, compile-time checked)

combine_output_cells expects [T; OUTPUT_LEN_NUM_U16S] (= 4). expand_to_rv64_block returns [T; BLOCK_FE_WIDTH] (= 4). These match because OUTPUT_LEN_NUM_BYTES / U16_CELL_SIZE = 8/2 = 4 = BLOCK_FE_WIDTH. If either constant changed independently, this would be a compile error, so it's safe. But the semantic meaning differs: the expand_to_rv64_block zero-extends the F_NUM_U16S = 2 output length cells to 4, and then combine_output_cells treats all 4 as u16 cells for the output key. The upper 2 cells are always zero since output_len is a u32 value stored in F_NUM_U16S = 2 cells. This is correct.

4. Sponge init-row range-check exemption is correct (Positive)

output/air.rs:332-337 (in the diff) — Data-row sponge cells get per-cell u16 range checks gated on local.is_valid - local.is_first, correctly exempting the init row. The init row's sponge_inputs are pinned by assert_array_eq against already-canonical deferral_idx and output_len columns.

5. def_fn.rs:91 — F::from_usize(output_ref.len()) silent wrapping for huge lengths (Low risk)

state[1] = F::from_usize(output_ref.len());

For BabyBear, values >= 2^31 would silently reduce mod P. The address_bits range check in the AIR prevents this in practice, but using F::from_u32(u32::try_from(output_ref.len()).unwrap()) would make the intent clearer and catch unexpected sizes earlier in host code. This is a minor defensive improvement, not a soundness issue.

6. e2e.rs test refactored to use generate_deferral_results directly (Good cleanup)

crates/continuations/src/tests/e2e.rs:134-145 — The compute_output_f_commit function was previously a manual reimplementation of the sponge hash. It now delegates to generate_deferral_results, which is the canonical implementation. This eliminates the risk of the test's hash diverging from the production code when the sponge rate changes. Well done.

7. RootCircuit::new validation and assert_user_pvs_shape (Good defensive change)

crates/continuations/src/circuit/root/mod.rs:41-55 — The manual new constructor with assert_user_pvs_shape replaces derive_new, upgrading scattered debug_assert! calls to a single assert! function. This is used in commit/air.rs, commit/trace.rs, memory/air.rs, and memory/trace.rs. Good hygiene that catches misconfigurations in release builds.

8. CUDA / Rust constant and column struct consistency (Correct)

def_types.h mirrors every constant from utils.rs: COMMIT_NUM_U16S, OUTPUT_LEN_NUM_U16S, OUTPUT_TOTAL_NUM_U16S, SPONGE_BYTES_PER_ROW, SPONGE_ROW_MEMORY_OPS, F_NUM_U16S, RV64_PTR_U16S. The DeferralOutputCols<T> and DeferralCallCoreCols<T> / DeferralCallAdapterCols<T> structs in CUDA match the Rust #[repr(C)] layouts. sizeof assertions guard against drift. The helper functions (pack_u8_pairs_le, u32_bytes_to_le_u16_cells, scale_u16_high_cell, scale_output_len, scale_rv64_ptr_from_u32_bytes) mirror their Rust counterparts.

9. bitwise_op_lookup fully removed from deferral extension (Clean removal)

The BitwiseOperationLookupBus / BitwiseOperationLookupChip dependency has been completely removed from the deferral extension: extension/mod.rs no longer creates or looks up bitwise chips, cuda_abi.rs drops the d_bitwise parameter, and all tests drop bitwise periphery. The call chip still uses the canonicity sub-AIR (which was already not using bitwise), and the output chip's bitwise usage is replaced by VariableRangeCheckerBus range checks. This is a clean factoring.

10. is_eq.rs modular chip fix (Tangential but correct)

extensions/algebra/circuit/src/modular_chip/is_eq.rs — The setup-row handling is fixed: during setup, c may equal the modulus (it's the modulus itself), so the c < modulus assertion is correctly skipped. The c_diff_idx fallback finds the first differing limb or defaults to 0, and uses wrapping_sub to avoid panic when c == modulus. The c_lt_mark is forced to F::TWO during setup to avoid the single-diff-index optimization colliding with the setup row's different semantics. This looks like a necessary fix for setup correctness with u16 limbs.

11. Adapter ptr_to_u16_limbs renamed to ptr_to_field_u16_limbs (Minor, in riscv-adapters)

vec_heap_u16.rs and vec_heap_branch_u16.rs update the function name. The rename avoids confusion with the raw u16 version — ptr_to_field_u16_limbs returns [F; N] directly.

---

Addressing reviewer comments

@stephenh-axiom-xyz's comment about u8 vs u16: Several places (record types, output_len bytes) still use u8 in the record / host-side representation. This is intentional — the execution record captures byte-level data, and the trace filler packs into u16 cells. The column types (DeferralCallReads<T, T>, DeferralCallWrites<T, T>) are now u16-shaped.

@stephenh-axiom-xyz's comment about BitwiseOperationLookupAir for u16 ops: Correctly noted by @shuklaayush that the table size would need to be 2^32, making it impractical.

@stephenh-axiom-xyz's comment about recursion range checker: @shuklaayush noted this could be bumped to 16-bit. The current PR adds a dedicated RangeCheckerAir<U16_BITS> in the verify-stark subcircuit (lib.rs:108), which is clean but does add an extra AIR. A future PR could unify this with the recursion range checker.

@GunaDD's comment about multiple.elf: This is the pre-compiled ELF for the updated guest program — it's expected to be committed alongside the source change.

@GunaDD's comment about RootCircuit::new assertion: This upgrades existing debug_assert! checks to assert! and centralizes them. The requirements (num_user_pvs >= DIGEST_SIZE, multiple of DIGEST_SIZE, power-of-two leaf count) were always needed — they just weren't checked in release builds.

---

Summary

The PR is well-executed with consistent changes across Rust AIR, tracegen, CUDA, verify-stark, and continuations. The migration from byte cells to u16 cells is mechanically clean, and the doubled sponge absorption rate is correctly threaded through all layers. The is_eq.rs fix is a necessary companion change for setup-row correctness with u16 limbs. I didn't find any correctness bugs.

Verdict: Looks good to merge. The only actionable suggestion is the minor defensive F::from_u32(u32::try_from(...).unwrap()) in def_fn.rs:91.

[github-actions]

Claude finished @shuklaayush's task in 3m 33s —— View job

---

Code Review: PR #2808 — Switch to u16 limbs in deferral AIRs

• Gather context and read the full diff
• Review deferral call chip changes (air, trace, tests)
• Review deferral output chip changes (air, trace, execution, tests)
• Review canonicity sub-AIR changes
• Review utility functions and helpers
• Review CUDA tracegen changes
• Review verify-stark and continuations changes
• Review guest programs and integration tests
• Address reviewer comments from previous reviews
• Post final review

---

Reviewed all 35 changed files across Rust AIR, tracegen, CUDA, verify-stark, continuations, riscv-adapters, and the algebra is_eq fix. The migration from byte cells to u16 cells is mechanically clean and the doubled sponge absorption rate is correctly threaded through all layers. No correctness bugs found.

---

Findings

1. COMMIT_MEMORY_OPS derivation is semantically stale (Nit — numerically correct)

utils.rs:36: COMMIT_MEMORY_OPS is still defined as num_byte_memory_ops(COMMIT_NUM_BYTES) = 32 / MEMORY_BLOCK_BYTES = 4. But its only uses now call split_f_memory_ops::<_, COMMIT_NUM_U16S, COMMIT_MEMORY_OPS>, which operates on u16 cells — the const-assert inside split_f_memory_ops verifies COMMIT_NUM_U16S == COMMIT_MEMORY_OPS * BLOCK_FE_WIDTH (16 == 4×4). The value is correct because COMMIT_NUM_BYTES / MEMORY_BLOCK_BYTES == COMMIT_NUM_U16S / BLOCK_FE_WIDTH, but the derivation formula doesn't reflect the u16 migration. Changing to num_f_memory_ops(COMMIT_NUM_U16S) would be cleaner and prevent confusion if these constants ever diverged.

2. Missing per-cell u16 range checks on input_commit reads is intentional (Confirmed correct)

call/air.rs:167-176 range-checks only the canonicity remainder values for input_commit, while output_commit and output_len get both canonicity RCs and per-cell u16 RCs (lines 181-191). This is correct: input_commit is read from RV64_MEMORY_AS via the memory bridge, so the u16 memory bus guarantees cell canonicity. output_commit and output_len are written, so the chip must prove the written values are canonical u16s.

3. is_eq.rs setup-row fix is correct and necessary (Companion fix)

extensions/algebra/circuit/src/modular_chip/is_eq.rs:402-427: During setup, the record's c carries the modulus value itself (not a value < modulus). With u16 limbs, the previous assert!(c_cmp) would fire since c == modulus. The fix:

• Skips c < modulus assertion during setup.
• Forces b_diff_idx = READ_LIMBS (out-of-range sentinel) and searches c_diff_idx via reverse scan with .unwrap_or(0).
• Forces c_lt_mark = F::TWO during setup, avoiding the single-diff-index optimization path that would conflate b and c canonicity.
• Uses wrapping_sub for c_lt_diff since c[i] == modulus[i] during setup yields 0 via wrapping.

The execution side (execute_e12_impl) is also correctly guarded with if !IS_SETUP (line 730).

4. def_fn.rs:91 — F::from_usize upgraded to F::from_u32 (Addressed)

The latest commit now uses F::from_u32(u32::try_from(output_ref.len()).unwrap()), which catches unexpected sizes earlier. This addresses the concern from previous reviews.

5. Sponge init-row range check exemption is correct (Positive)

output/air.rs:334-339: Data-row sponge cells get per-cell u16 range checks gated on local.is_valid - local.is_first, correctly exempting the init row. The init row's sponge_inputs are pinned by assert_array_eq against already-canonical deferral_idx and output_len columns — no separate range check needed.

6. Verify-stark RangeCheckerAir<U16_BITS> is a clean addition

guest-libs/verify-stark/circuit/src/lib.rs:108-110 and trace.rs:47-50: The output commit range checks now use a dedicated RangeCheckerAir<U16_BITS> proving context instead of being aggregated into the range_inputs vec. The trace generator uses RangeCheckerCpuTraceGenerator to collect counts and generates the range checker trace row-major. trace.rs:142 correctly returns range_inputs: vec![] since the range checker now has its own AIR. As noted in reviewer comments, a future PR could unify this with the recursion range checker by bumping it to 16-bit.

7. combine_output_cells + expand_to_rv64_block size coupling is compile-time safe

Both call/air.rs:451 and output/air.rs:307 pass output_len_full: [AB::Expr; BLOCK_FE_WIDTH] (= 4 elements, zero-extended from F_NUM_U16S = 2) to combine_output_cells which expects [T; OUTPUT_LEN_NUM_U16S] (= 4). The equality OUTPUT_LEN_NUM_U16S == BLOCK_FE_WIDTH holds because 8 / 2 == 4, and any mismatch would be a compile error.

8. CUDA and Rust constant + struct consistency (Correct)

def_types.h mirrors every u16-cell constant from utils.rs: COMMIT_NUM_U16S, OUTPUT_LEN_NUM_U16S, OUTPUT_TOTAL_NUM_U16S, SPONGE_BYTES_PER_ROW, SPONGE_ROW_MEMORY_OPS, F_NUM_U16S, RV64_PTR_U16S. The helper functions (pack_u8_pairs_le, u32_bytes_to_le_u16_cells, scale_u16_high_cell, scale_output_len, scale_rv64_ptr_from_u32_bytes) have equivalent Rust counterparts. The CUDA column structs (DeferralOutputCols, DeferralCallCoreCols, DeferralCallAdapterCols) match the Rust #[repr(C)] layouts, and sizeof assertions guard against drift.

9. BitwiseOperationLookup fully removed from deferral (Clean removal)

extension/mod.rs no longer creates/looks up bitwise chips, cuda_abi.rs drops d_bitwise, extension/cuda.rs drops get_or_create_bitwise_op_lookup, all tests drop bitwise periphery. The canonicity sub-AIR and per-cell range checks now use VariableRangeCheckerBus exclusively.

10. e2e.rs test correctly delegates to generate_deferral_results (Good cleanup)

crates/continuations/src/tests/e2e.rs:134-145: compute_output_f_commit now delegates to generate_deferral_results + deferral_poseidon2_chip() instead of reimplementing the sponge hash. This eliminates the risk of the test diverging from production when the sponge rate changes.

11. Guest test outputs correctly updated for 16-byte alignment

All guest programs (single.rs, multiple.rs in both deferral/tests/ and continuations/) extend expected outputs from 8 to 16 bytes. The new test output_raw_len_must_be_sponge_row_aligned verifies the panic path. The deferral/tests/src/lib.rs input arrays are extended to 16 bytes.

---

Addressing reviewer comments

• @stephenh-axiom-xyz — u8 vs u16 in records: The byte-shaped record types (DeferralCallReadsBytes, DeferralCallWritesBytes) are intentional. The execution record captures byte-level data; the trace filler packs bytes into u16 column cells. The column types are now u16-shaped.

• @stephenh-axiom-xyz — BitwiseOperationLookupAir for u16 ops: Correctly noted by @shuklaayush that the table would need 2^32 entries, making it impractical.

• @stephenh-axiom-xyz — recursion range checker: The current PR adds RangeCheckerAir<U16_BITS> in verify-stark. A future PR could unify with the recursion range checker.

• @GunaDD — multiple.elf: Pre-compiled ELF for the updated guest program — expected to be committed alongside the source change.

• @GunaDD — RootCircuit::new assertion: Upgrades existing debug_assert! to assert! via centralized assert_user_pvs_shape. The requirements were always needed but not checked in release builds.

---

Summary

The PR is well-executed. The u16 cell migration is consistent across all layers, the doubled sponge rate is correctly factored through shared constants, and the is_eq.rs companion fix is a necessary correction for setup-row correctness with u16 limbs. The only actionable nit is the COMMIT_MEMORY_OPS derivation formula (finding #1), which doesn't affect correctness.

Verdict: Looks good to merge.

[github-actions]

group	app.proof_time_ms	app.cycles	leaf.proof_time_ms
fibonacci	1,555	4,000,051	438
keccak	13,965	14,365,133	2,378
sha2_bench	9,193	11,167,961	1,426
regex	1,586	4,090,656	356
ecrecover	488	112,210	268
pairing	596	592,827	253
kitchen_sink	1,991	1,979,971	404

Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights.

Commit: d457878

Benchmark Workflow