8390826: RISC-V: Use dedicated vector mask logical instructions - #32480
8390826: RISC-V: Use dedicated vector mask logical instructions#32480DingliZhang wants to merge 1 commit into
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| instruct vmask_xnorI(vRegMask dst, vRegMask src1, vRegMask src2, immI_M1 m1) %{ | ||
| match(Set dst (XorVMask (XorVMask src1 src2) (MaskAll m1))); | ||
| match(Set dst (XorVMask src1 (XorVMask src2 (MaskAll m1)))); |
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Question: There are two matchings for this instruct. But seems the newly-add IR test only covered one of them, right? I am wondering if we really need both of them.
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| instruct vmask_xnorL(vRegMask dst, vRegMask src1, vRegMask src2, immL_M1 m1) %{ | ||
| match(Set dst (XorVMask (XorVMask src1 src2) (MaskAll m1))); | ||
| match(Set dst (XorVMask src1 (XorVMask src2 (MaskAll m1)))); |
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Hi, please consider.
This is a follow-up to JDK-8390101.
On RISC-V, several VectorMask logical operations involving an all-bits-set mask are currently emitted as sequences of multiple RVV mask instructions. These include:
RVV provides mask logical instructions that can implement these operations directly.
This change adds RISC-V C2 match rules to emit:
The rules cover byte, short, int, and long vector element types and replace multi-instruction mask logical sequences with a single RVV mask instruction.
Testing
MaskLogicOperationsBenchmarkon sg2044:compiler/vectorapi/AllBitsSetVectorMatchRuleTest.javapassed on sg2044test/jdk/jdk/incubator/vectorpassed on sg2044tier1on sg2044Progress
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