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8391052: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length - #32472

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8391052: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length#32472
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@zny666 zny666 commented Aug 20, 2026

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There is currently no electronicCodeBook (ECB) AES stub on RISC-V, so ElectronicCodeBook falls back to a Java loop over the per-block intrinsic: implECBEncrypt/implECBDecrypt call embeddedCipher.encryptBlock/decryptBlock once per 16-byte block, and each per-block stub call reloads all round keys (11-15 x vle32 + vrev8) before doing the 10-14 rounds.

This patch adds the two missing ECB stubs only. The existing single-block, CBC and CTR stubs are not touched.

  • The ECB loops scale to the vector length with LMUL=1: the bulk loop runs m1/e32 with VL = VLMAX (register form vsetvli), so one loop shape serves every VLEN - each iteration processes VLEN/128 AES blocks (1 at VLEN=128, 2 at VLEN=256, 4 at VLEN=512), with a single-block m1 tail for the remainder. No compile-time VLEN dispatch.

  • Round keys are loaded once per call, right-aligned in v4..v18 (AES-128/192/256 -> v8..v18 / v6..v18 / v4..v18), with runtime key-size dispatch, so one unrolled round body serves all three key sizes.

  • The Zvkned .vs instruction forms (broadcasting an m1 round key to all element groups of a VL>4 data register) are added to the assembler; the existing .vv forms would need a key splat for multi-group data.

Performance (JMH average time, single pre-initialized Cipher.doFinal per op; same-machine, same-JDK-version A/B, patched vs unpatched), on a RVV 1.0 implementation with VLEN=256 and Zvkned, measured with perf cycles. Values are speedup ratios (unpatched / patched cycles per op):

AES-128:

Benchmark 256B 1KB 4KB 16KB
ecbEncrypt 3.41x 4.26x 4.58x 4.72x
ecbDecrypt 3.50x 4.36x 4.66x 4.80x

AES-192:

Benchmark 256B 1KB 4KB 16KB
ecbEncrypt 3.49x 4.26x 4.50x 4.63x
ecbDecrypt 3.50x 4.34x 4.58x 4.69x

AES-256:

Benchmark 256B 1KB 4KB 16KB
ecbEncrypt 3.49x 4.15x 4.46x 4.55x
ecbDecrypt 3.41x 4.26x 4.52x 4.62x

Absolute cycles/op (patched vs unpatched):

Benchmark unpatched patched
ecbEncrypt/128/16KB 70942 15019
ecbEncrypt/256/16KB 87320 19206
ecbDecrypt/128/16KB 72126 15029
ecbDecrypt/256/16KB 88498 19178

Instructions per op drop by ~88% (e.g. ecbEncrypt/128/16KB: 87177 -> 10385): the Java per-block loop and the per-block round-key reload are gone, and the round latency chain is shared across the blocks of each batch. At small sizes the fixed per-doFinal entry cost is a larger share of the total, so the speedup grows from ~3.4x at 256B to ~4.7x at 16KB.

Testing: AES/ECB known-answer vectors (AES-128/192/256, encrypt and decrypt) plus randomized round-trips (NoPadding and PKCS5Padding, lengths 16B-8KB) pass with the intrinsic enabled, with -XX:-UseAESIntrinsics (identical results) on qemu-riscv64 at vlen=128, vlen=256 and vlen=512, and on VLEN=256 hardware. Stub generation is confirmed via -XX:+PrintStubCode (both electronicCodeBook stubs present; absent without this patch). The performance numbers above are measured on VLEN=256 hardware only; the vlen=128/512 paths are verified for correctness, not for performance.


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  • JDK-8391052: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length (Enhancement - P4)

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@bridgekeeper bridgekeeper Bot added the oca Needs verification of OCA signatory status label Aug 20, 2026
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@openjdk openjdk Bot added the hotspot hotspot-dev@openjdk.org label Aug 20, 2026
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@zny666 Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

… vector length

There is currently no electronicCodeBook AES stub on RISC-V, so
ElectronicCodeBook falls back to a Java loop over the per-block
intrinsic. This change adds the two missing ECB stubs
(encrypt/decrypt), keeping the existing block/CBC/CTR stubs untouched.

The stubs scale to the vector length with LMUL=1 only: the bulk loop
runs m1/e32 with VL = VLMAX (register form vsetvli), so one loop shape
serves every VLEN - each iteration processes VLEN/128 AES blocks (1 at
VLEN=128, 2 at VLEN=256, 4 at VLEN=512), with a single-block m1 tail
for the remainder.

Round keys are loaded once as m1 groups (vle32 + vrev8) and applied
with the Zvkned .vs broadcast forms, whose encodings are added to the
assembler; .vs lets one m1 round key serve all element groups of the
VL>4 data register without a key splat. Key size (AES-128/192/256) is
dispatched at runtime on the key array length, with round keys
right-aligned in v4..v18 so one unrolled round body serves all three
key sizes.

Tested with an AES/ECB known-answer and round-trip suite (AES-128/192/
256, NoPadding and PKCS5Padding, lengths 16B-8KB) on qemu-riscv64 with
vlen=128, vlen=256 and vlen=512, both with the intrinsic enabled and
with -XX:-UseAESIntrinsics (results identical).
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@zny666 Please do not rebase or force-push to an active PR as it invalidates existing review comments. Note for future reference, the bots always squash all changes into a single commit automatically as part of the integration. See OpenJDK Developers’ Guide for more information.

@zny666 zny666 changed the title 8390755: RISC-V: scale AES ECB, CTR and CBC stubs to the vector length with LMUL=2 batching 8390755: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length Aug 25, 2026
@zny666 zny666 changed the title 8390755: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length 8391052: RISC-V: Add electronicCodeBook (ECB) AES stubs scaled to the vector length Aug 25, 2026
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