Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
db		db
incremental_db		incremental_db
LEIA-ME.txt		LEIA-ME.txt
LICENSE		LICENSE
README.md		README.md
a.out		a.out
bcd7convert.v		bcd7convert.v
bcd7convert.v.bak		bcd7convert.v.bak
clock1unit.v		clock1unit.v
contadorbcd.v		contadorbcd.v
contadorbcd.v.bak		contadorbcd.v.bak
displayModule.v		displayModule.v
displayModule.v.bak		displayModule.v.bak
divisorClock.v		divisorClock.v
divisorClock.v.bak		divisorClock.v.bak
documentacao.pdf		documentacao.pdf
estadosJflap.jflap		estadosJflap.jflap
estadosJflap.jpg		estadosJflap.jpg
testbench.v		testbench.v
urna.v		urna.v
urna.v.bak		urna.v.bak
urnaEletronica.vcd		urnaEletronica.vcd
urnatp.asm.rpt		urnatp.asm.rpt
urnatp.done		urnatp.done
urnatp.eda.rpt		urnatp.eda.rpt
urnatp.fit.rpt		urnatp.fit.rpt
urnatp.fit.smsg		urnatp.fit.smsg
urnatp.fit.summary		urnatp.fit.summary
urnatp.flow.rpt		urnatp.flow.rpt
urnatp.htm		urnatp.htm
urnatp.jdi		urnatp.jdi
urnatp.map.rpt		urnatp.map.rpt
urnatp.map.smsg		urnatp.map.smsg
urnatp.map.summary		urnatp.map.summary
urnatp.pin		urnatp.pin
urnatp.qpf		urnatp.qpf
urnatp.qsf		urnatp.qsf
urnatp.qws		urnatp.qws
urnatp.sdc		urnatp.sdc
urnatp.sld		urnatp.sld
urnatp.sof		urnatp.sof
urnatp.sta.rpt		urnatp.sta.rpt
urnatp.sta.summary		urnatp.sta.summary
urnatp.v		urnatp.v
urnatp.v.bak		urnatp.v.bak
urnatp_assignment_defaults.qdf		urnatp_assignment_defaults.qdf
votoValido.v		votoValido.v
votoValido.v.bak		votoValido.v.bak

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TP2-ISL-URNA

About

Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.

fpga verilog verilog-hdl fpga-firmware altera-fpga verilog-simulator verilog-project altera-de2

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MIT license