|
28 | 28 |
|
29 | 29 | #include <asm/cpu_device_id.h> |
30 | 30 | #include <asm/intel-family.h> |
31 | | -#include <asm/iosf_mbi.h> |
32 | 31 | #include <asm/msr.h> |
33 | 32 |
|
34 | 33 | /* bitmasks for RAPL MSRs, used by primitive access functions */ |
@@ -212,8 +211,6 @@ static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim) |
212 | 211 | #define power_zone_to_rapl_domain(_zone) \ |
213 | 212 | container_of(_zone, struct rapl_domain, power_zone) |
214 | 213 |
|
215 | | -static const struct rapl_defaults *defaults_msr; |
216 | | - |
217 | 214 | static const struct rapl_defaults *get_defaults(struct rapl_package *rp) |
218 | 215 | { |
219 | 216 | return rp->priv->defaults; |
@@ -759,7 +756,6 @@ static int rapl_config(struct rapl_package *rp) |
759 | 756 | /* MMIO I/F shares the same register layout as MSR registers */ |
760 | 757 | case RAPL_IF_MMIO: |
761 | 758 | case RAPL_IF_MSR: |
762 | | - rp->priv->defaults = defaults_msr; |
763 | 759 | rp->priv->rpi = (void *)rpi_msr; |
764 | 760 | break; |
765 | 761 | case RAPL_IF_TPMI: |
@@ -947,34 +943,6 @@ int rapl_default_check_unit(struct rapl_domain *rd) |
947 | 943 | } |
948 | 944 | EXPORT_SYMBOL_NS_GPL(rapl_default_check_unit, "INTEL_RAPL"); |
949 | 945 |
|
950 | | -static int rapl_check_unit_atom(struct rapl_domain *rd) |
951 | | -{ |
952 | | - struct reg_action ra; |
953 | | - u32 value; |
954 | | - |
955 | | - ra.reg = rd->regs[RAPL_DOMAIN_REG_UNIT]; |
956 | | - ra.mask = ~0; |
957 | | - if (rd->rp->priv->read_raw(get_rid(rd->rp), &ra, false)) { |
958 | | - pr_err("Failed to read power unit REG 0x%llx on %s:%s, exit.\n", |
959 | | - ra.reg.val, rd->rp->name, rd->name); |
960 | | - return -ENODEV; |
961 | | - } |
962 | | - |
963 | | - value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET; |
964 | | - rd->energy_unit = ENERGY_UNIT_SCALE * (1ULL << value); |
965 | | - |
966 | | - value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET; |
967 | | - rd->power_unit = (1ULL << value) * MILLIWATT_PER_WATT; |
968 | | - |
969 | | - value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET; |
970 | | - rd->time_unit = USEC_PER_SEC >> value; |
971 | | - |
972 | | - pr_debug("Atom %s:%s energy=%dpJ, time=%dus, power=%duW\n", |
973 | | - rd->rp->name, rd->name, rd->energy_unit, rd->time_unit, rd->power_unit); |
974 | | - |
975 | | - return 0; |
976 | | -} |
977 | | - |
978 | 946 | static void power_limit_irq_save_cpu(void *info) |
979 | 947 | { |
980 | 948 | u32 l, h = 0; |
@@ -1055,30 +1023,6 @@ void rapl_default_set_floor_freq(struct rapl_domain *rd, bool mode) |
1055 | 1023 | } |
1056 | 1024 | EXPORT_SYMBOL_NS_GPL(rapl_default_set_floor_freq, "INTEL_RAPL"); |
1057 | 1025 |
|
1058 | | -static void set_floor_freq_atom(struct rapl_domain *rd, bool enable) |
1059 | | -{ |
1060 | | - static u32 power_ctrl_orig_val; |
1061 | | - const struct rapl_defaults *defaults = get_defaults(rd->rp); |
1062 | | - u32 mdata; |
1063 | | - |
1064 | | - if (!defaults->floor_freq_reg_addr) { |
1065 | | - pr_err("Invalid floor frequency config register\n"); |
1066 | | - return; |
1067 | | - } |
1068 | | - |
1069 | | - if (!power_ctrl_orig_val) |
1070 | | - iosf_mbi_read(BT_MBI_UNIT_PMC, MBI_CR_READ, |
1071 | | - defaults->floor_freq_reg_addr, |
1072 | | - &power_ctrl_orig_val); |
1073 | | - mdata = power_ctrl_orig_val; |
1074 | | - if (enable) { |
1075 | | - mdata &= ~GENMASK(14, 8); |
1076 | | - mdata |= BIT(8); |
1077 | | - } |
1078 | | - iosf_mbi_write(BT_MBI_UNIT_PMC, MBI_CR_WRITE, |
1079 | | - defaults->floor_freq_reg_addr, mdata); |
1080 | | -} |
1081 | | - |
1082 | 1026 | u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_raw) |
1083 | 1027 | { |
1084 | 1028 | u64 f, y; /* fraction and exp. used for time unit */ |
@@ -1112,149 +1056,6 @@ u64 rapl_default_compute_time_window(struct rapl_domain *rd, u64 value, bool to_ |
1112 | 1056 | } |
1113 | 1057 | EXPORT_SYMBOL_NS_GPL(rapl_default_compute_time_window, "INTEL_RAPL"); |
1114 | 1058 |
|
1115 | | -static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value, |
1116 | | - bool to_raw) |
1117 | | -{ |
1118 | | - if (to_raw) |
1119 | | - return div64_u64(value, rd->time_unit); |
1120 | | - |
1121 | | - /* |
1122 | | - * Atom time unit encoding is straight forward val * time_unit, |
1123 | | - * where time_unit is default to 1 sec. Never 0. |
1124 | | - */ |
1125 | | - return (value) ? value * rd->time_unit : rd->time_unit; |
1126 | | -} |
1127 | | - |
1128 | | -static const struct rapl_defaults rapl_defaults_core = { |
1129 | | - .floor_freq_reg_addr = 0, |
1130 | | - .check_unit = rapl_default_check_unit, |
1131 | | - .set_floor_freq = rapl_default_set_floor_freq, |
1132 | | - .compute_time_window = rapl_default_compute_time_window, |
1133 | | -}; |
1134 | | - |
1135 | | -static const struct rapl_defaults rapl_defaults_hsw_server = { |
1136 | | - .check_unit = rapl_default_check_unit, |
1137 | | - .set_floor_freq = rapl_default_set_floor_freq, |
1138 | | - .compute_time_window = rapl_default_compute_time_window, |
1139 | | - .dram_domain_energy_unit = 15300, |
1140 | | -}; |
1141 | | - |
1142 | | -static const struct rapl_defaults rapl_defaults_spr_server = { |
1143 | | - .check_unit = rapl_default_check_unit, |
1144 | | - .set_floor_freq = rapl_default_set_floor_freq, |
1145 | | - .compute_time_window = rapl_default_compute_time_window, |
1146 | | - .psys_domain_energy_unit = NANOJOULE_PER_JOULE, |
1147 | | - .spr_psys_bits = true, |
1148 | | -}; |
1149 | | - |
1150 | | -static const struct rapl_defaults rapl_defaults_byt = { |
1151 | | - .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT, |
1152 | | - .check_unit = rapl_check_unit_atom, |
1153 | | - .set_floor_freq = set_floor_freq_atom, |
1154 | | - .compute_time_window = rapl_compute_time_window_atom, |
1155 | | -}; |
1156 | | - |
1157 | | -static const struct rapl_defaults rapl_defaults_tng = { |
1158 | | - .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG, |
1159 | | - .check_unit = rapl_check_unit_atom, |
1160 | | - .set_floor_freq = set_floor_freq_atom, |
1161 | | - .compute_time_window = rapl_compute_time_window_atom, |
1162 | | -}; |
1163 | | - |
1164 | | -static const struct rapl_defaults rapl_defaults_ann = { |
1165 | | - .floor_freq_reg_addr = 0, |
1166 | | - .check_unit = rapl_check_unit_atom, |
1167 | | - .set_floor_freq = NULL, |
1168 | | - .compute_time_window = rapl_compute_time_window_atom, |
1169 | | -}; |
1170 | | - |
1171 | | -static const struct rapl_defaults rapl_defaults_cht = { |
1172 | | - .floor_freq_reg_addr = 0, |
1173 | | - .check_unit = rapl_check_unit_atom, |
1174 | | - .set_floor_freq = NULL, |
1175 | | - .compute_time_window = rapl_compute_time_window_atom, |
1176 | | -}; |
1177 | | - |
1178 | | -static const struct rapl_defaults rapl_defaults_amd = { |
1179 | | - .check_unit = rapl_default_check_unit, |
1180 | | -}; |
1181 | | - |
1182 | | -static const struct x86_cpu_id rapl_ids[] __initconst = { |
1183 | | - X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core), |
1184 | | - X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core), |
1185 | | - |
1186 | | - X86_MATCH_VFM(INTEL_IVYBRIDGE, &rapl_defaults_core), |
1187 | | - X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &rapl_defaults_core), |
1188 | | - |
1189 | | - X86_MATCH_VFM(INTEL_HASWELL, &rapl_defaults_core), |
1190 | | - X86_MATCH_VFM(INTEL_HASWELL_L, &rapl_defaults_core), |
1191 | | - X86_MATCH_VFM(INTEL_HASWELL_G, &rapl_defaults_core), |
1192 | | - X86_MATCH_VFM(INTEL_HASWELL_X, &rapl_defaults_hsw_server), |
1193 | | - |
1194 | | - X86_MATCH_VFM(INTEL_BROADWELL, &rapl_defaults_core), |
1195 | | - X86_MATCH_VFM(INTEL_BROADWELL_G, &rapl_defaults_core), |
1196 | | - X86_MATCH_VFM(INTEL_BROADWELL_D, &rapl_defaults_core), |
1197 | | - X86_MATCH_VFM(INTEL_BROADWELL_X, &rapl_defaults_hsw_server), |
1198 | | - |
1199 | | - X86_MATCH_VFM(INTEL_SKYLAKE, &rapl_defaults_core), |
1200 | | - X86_MATCH_VFM(INTEL_SKYLAKE_L, &rapl_defaults_core), |
1201 | | - X86_MATCH_VFM(INTEL_SKYLAKE_X, &rapl_defaults_hsw_server), |
1202 | | - X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core), |
1203 | | - X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core), |
1204 | | - X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core), |
1205 | | - X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core), |
1206 | | - X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core), |
1207 | | - X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core), |
1208 | | - X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server), |
1209 | | - X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server), |
1210 | | - X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core), |
1211 | | - X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core), |
1212 | | - X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core), |
1213 | | - X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core), |
1214 | | - X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core), |
1215 | | - X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core), |
1216 | | - X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core), |
1217 | | - X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core), |
1218 | | - X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core), |
1219 | | - X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core), |
1220 | | - X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core), |
1221 | | - X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core), |
1222 | | - X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core), |
1223 | | - X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core), |
1224 | | - X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server), |
1225 | | - X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server), |
1226 | | - X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core), |
1227 | | - X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core), |
1228 | | - X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core), |
1229 | | - X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core), |
1230 | | - X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core), |
1231 | | - X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core), |
1232 | | - X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core), |
1233 | | - X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core), |
1234 | | - X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core), |
1235 | | - |
1236 | | - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt), |
1237 | | - X86_MATCH_VFM(INTEL_ATOM_AIRMONT, &rapl_defaults_cht), |
1238 | | - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID, &rapl_defaults_tng), |
1239 | | - X86_MATCH_VFM(INTEL_ATOM_SILVERMONT_MID2, &rapl_defaults_ann), |
1240 | | - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT, &rapl_defaults_core), |
1241 | | - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_PLUS, &rapl_defaults_core), |
1242 | | - X86_MATCH_VFM(INTEL_ATOM_GOLDMONT_D, &rapl_defaults_core), |
1243 | | - X86_MATCH_VFM(INTEL_ATOM_TREMONT, &rapl_defaults_core), |
1244 | | - X86_MATCH_VFM(INTEL_ATOM_TREMONT_D, &rapl_defaults_core), |
1245 | | - X86_MATCH_VFM(INTEL_ATOM_TREMONT_L, &rapl_defaults_core), |
1246 | | - |
1247 | | - X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &rapl_defaults_hsw_server), |
1248 | | - X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &rapl_defaults_hsw_server), |
1249 | | - |
1250 | | - X86_MATCH_VENDOR_FAM(AMD, 0x17, &rapl_defaults_amd), |
1251 | | - X86_MATCH_VENDOR_FAM(AMD, 0x19, &rapl_defaults_amd), |
1252 | | - X86_MATCH_VENDOR_FAM(AMD, 0x1A, &rapl_defaults_amd), |
1253 | | - X86_MATCH_VENDOR_FAM(HYGON, 0x18, &rapl_defaults_amd), |
1254 | | - {} |
1255 | | -}; |
1256 | | -MODULE_DEVICE_TABLE(x86cpu, rapl_ids); |
1257 | | - |
1258 | 1059 | /* Read once for all raw primitive data for domains */ |
1259 | 1060 | static void rapl_update_domain_data(struct rapl_package *rp) |
1260 | 1061 | { |
@@ -2266,40 +2067,13 @@ static struct notifier_block rapl_pm_notifier = { |
2266 | 2067 | .notifier_call = rapl_pm_callback, |
2267 | 2068 | }; |
2268 | 2069 |
|
2269 | | -static struct platform_device *rapl_msr_platdev; |
2270 | | - |
2271 | 2070 | static int __init rapl_init(void) |
2272 | 2071 | { |
2273 | | - const struct x86_cpu_id *id; |
2274 | | - int ret; |
2275 | | - |
2276 | | - id = x86_match_cpu(rapl_ids); |
2277 | | - if (id) { |
2278 | | - defaults_msr = (const struct rapl_defaults *)id->driver_data; |
2279 | | - |
2280 | | - rapl_msr_platdev = platform_device_alloc("intel_rapl_msr", 0); |
2281 | | - if (!rapl_msr_platdev) |
2282 | | - return -ENOMEM; |
2283 | | - |
2284 | | - ret = platform_device_add(rapl_msr_platdev); |
2285 | | - if (ret) { |
2286 | | - platform_device_put(rapl_msr_platdev); |
2287 | | - return ret; |
2288 | | - } |
2289 | | - } |
2290 | | - |
2291 | | - ret = register_pm_notifier(&rapl_pm_notifier); |
2292 | | - if (ret && rapl_msr_platdev) { |
2293 | | - platform_device_del(rapl_msr_platdev); |
2294 | | - platform_device_put(rapl_msr_platdev); |
2295 | | - } |
2296 | | - |
2297 | | - return ret; |
| 2072 | + return register_pm_notifier(&rapl_pm_notifier); |
2298 | 2073 | } |
2299 | 2074 |
|
2300 | 2075 | static void __exit rapl_exit(void) |
2301 | 2076 | { |
2302 | | - platform_device_unregister(rapl_msr_platdev); |
2303 | 2077 | unregister_pm_notifier(&rapl_pm_notifier); |
2304 | 2078 | } |
2305 | 2079 |
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