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Merge tag 'tegra-for-7.1-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
arm64: tegra: Device tree changes for v7.1-rc1 Various fixes and new additions across a number of devices. GPIO and PCI are enabled on Tegra264 and the Jetson AGX Thor Developer Kit, allowing it to boot via network and mass storage. * tag 'tegra-for-7.1-arm64-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: arm64: tegra: Add Tegra264 GPIO controllers arm64: tegra: smaug: Enable SPI-NOR flash arm64: tegra: Add Jetson AGX Thor Developer Kit support arm64: tegra: Add PCI controllers on Tegra264 arm64: tegra: Fix RTC aliases arm64: tegra: Drop redundant clock and reset names for TSEC arm64: tegra: Fix snps,blen properties dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
2 parents 9c5a544 + c70e6bc commit d619216

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Lines changed: 500 additions & 32 deletions

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‎Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml‎

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NVIDIA Tegra264 PCIe controller
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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properties:
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compatible:
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const: nvidia,tegra264-pcie
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reg:
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description: |
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Of the six PCIe controllers found on Tegra264, one (C0) is used for the
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internal GPU and the other five (C1-C5) are routed to connectors such as
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PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1
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through C5, but not for C0.
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minItems: 4
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items:
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- description: ECAM-compatible configuration space
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- description: application layer registers
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- description: transaction layer registers
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- description: privileged transaction layer registers
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- description: data link/physical layer registers (not available on C0)
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reg-names:
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minItems: 4
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items:
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- const: ecam
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- const: xal
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- const: xtl
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- const: xtl-pri
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- const: xpl
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interrupts:
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minItems: 1
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maxItems: 4
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dma-coherent: true
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nvidia,bpmp:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: |
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Must contain a pair of phandle (to the BPMP controller node) and
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controller ID. The following are the controller IDs for each controller:
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0: C0
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1: C1
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2: C2
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3: C3
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4: C4
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5: C5
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items:
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- items:
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- description: phandle to the BPMP controller node
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- description: PCIe controller ID
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maximum: 5
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required:
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- interrupt-map
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- interrupt-map-mask
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- iommu-map
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- msi-map
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- nvidia,bpmp
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pci@c000000 {
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compatible = "nvidia,tegra264-pcie";
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reg = <0xd0 0xb0000000 0x0 0x10000000>,
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<0x00 0x0c000000 0x0 0x00004000>,
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<0x00 0x0c004000 0x0 0x00001000>,
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<0x00 0x0c005000 0x0 0x00001000>;
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reg-names = "ecam", "xal", "xtl", "xtl-pri";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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linux,pci-domain = <0x00>;
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#interrupt-cells = <0x1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,
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<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,
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<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,
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<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;
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iommu-map = <0x0 &smmu2 0x10000 0x10000>;
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msi-map = <0x0 &its 0x210000 0x10000>;
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dma-coherent;
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ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,
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<0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,
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<0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;
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bus-range = <0x0 0xff>;
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nvidia,bpmp = <&bpmp 0>;
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};
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};
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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pci@8400000 {
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compatible = "nvidia,tegra264-pcie";
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reg = <0xa8 0xb0000000 0x0 0x10000000>,
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<0x00 0x08400000 0x0 0x00004000>,
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<0x00 0x08404000 0x0 0x00001000>,
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<0x00 0x08405000 0x0 0x00001000>,
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<0x00 0x08410000 0x0 0x00010000>;
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reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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linux,pci-domain = <0x01>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,
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<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,
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<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,
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<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;
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iommu-map = <0x0 &smmu1 0x10000 0x10000>;
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msi-map = <0x0 &its 0x110000 0x10000>;
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dma-coherent;
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ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,
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<0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,
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<0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;
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bus-range = <0x00 0xff>;
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nvidia,bpmp = <&bpmp 1>;
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};
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};

‎arch/arm64/boot/dts/nvidia/Makefile‎

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@@ -14,6 +14,7 @@ DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@
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DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@
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DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@
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DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@
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DTC_FLAGS_tegra264-p4071-0000+p3834-0008 := -@
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dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb
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dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb
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dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb
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dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb
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dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p4071-0000+p3834-0008.dtb

‎arch/arm64/boot/dts/nvidia/tegra210-smaug.dts‎

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};
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};
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spi@70410000 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <2>;
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spi-rx-bus-width = <2>;
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};
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};
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clk32k_in: clock-32k {
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compatible = "fixed-clock";
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clock-frequency = <32768>;

‎arch/arm64/boot/dts/nvidia/tegra210.dtsi‎

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reg = <0x0 0x54500000 0x0 0x00040000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&tegra_car TEGRA210_CLK_TSECB>;
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clock-names = "tsec";
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resets = <&tegra_car 206>;
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reset-names = "tsec";
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status = "disabled";
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};
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‎arch/arm64/boot/dts/nvidia/tegra234-p3701.dtsi‎

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mmc0 = "/bus@0/mmc@3460000";
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mmc1 = "/bus@0/mmc@3400000";
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rtc0 = "/bpmp/i2c/pmic@3c";
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rtc1 = "/bus@0/rtc@c2a0000";
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};
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bus@0 {

‎arch/arm64/boot/dts/nvidia/tegra234-p3767.dtsi‎

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aliases {
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mmc0 = "/bus@0/mmc@3400000";
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rtc0 = "/bpmp/i2c/pmic@3c";
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rtc1 = "/bus@0/rtc@c2a0000";
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};
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bus@0 {

‎arch/arm64/boot/dts/nvidia/tegra234.dtsi‎

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snps,axi-config = <&mgbe0_axi_setup>;
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mgbe0_axi_setup: stmmac-axi-config {
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snps,blen = <256 128 64 32>;
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snps,blen = <256 128 64 32 0 0 0>;
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snps,rd_osr_lmt = <63>;
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snps,wr_osr_lmt = <63>;
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};
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snps,axi-config = <&mgbe1_axi_setup>;
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mgbe1_axi_setup: stmmac-axi-config {
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snps,blen = <256 128 64 32>;
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snps,blen = <256 128 64 32 0 0 0>;
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snps,rd_osr_lmt = <63>;
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snps,wr_osr_lmt = <63>;
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};
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snps,axi-config = <&mgbe2_axi_setup>;
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mgbe2_axi_setup: stmmac-axi-config {
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snps,blen = <256 128 64 32>;
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snps,blen = <256 128 64 32 0 0 0>;
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snps,rd_osr_lmt = <63>;
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snps,wr_osr_lmt = <63>;
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};

‎arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts‎

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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/dts-v1/;
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// module files must be included first
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#include "tegra264-p3834-0008.dtsi"
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#include "tegra264-p4071-0000+p3834.dtsi"
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/ {
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model = "NVIDIA Jetson AGX Thor Developer Kit";
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compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264";
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};

‎arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi‎

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// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/ {
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aliases {
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serial0 = &{/bus@0/serial@c4e0000};
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serial1 = &{/bus@0/serial@c5a0000};
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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};

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