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Prathamesh Shetethierryreding
Prathamesh Shete
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thierryreding
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arm64: tegra: Add Tegra264 GPIO controllers
Add device tree nodes for MAIN, AON and UPHY GPIO controller instances. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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‎arch/arm64/boot/dts/nvidia/tegra264.dtsi‎

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3277,6 +3277,50 @@
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status = "disabled";
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};
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gpio_main: gpio@c300000 {
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compatible = "nvidia,tegra264-gpio";
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reg = <0x00 0x0c300000 0x0 0x4000>,
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<0x00 0x0c310000 0x0 0x4000>;
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reg-names = "security", "gpio";
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wakeup-parent = <&pmc>;
3286+
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
3320+
interrupt-controller;
3321+
#interrupt-cells = <2>;
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};
3323+
32803324
serial@c4e0000 {
32813325
compatible = "nvidia,tegra264-utc";
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reg = <0x0 0x0c4e0000 0x0 0x8000>,
@@ -3347,6 +3391,22 @@
33473391
#interrupt-cells = <2>;
33483392
interrupt-controller;
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};
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3395+
gpio_aon: gpio@cf00000 {
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compatible = "nvidia,tegra264-gpio-aon";
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reg = <0x0 0x0cf00000 0x0 0x10000>,
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<0x0 0x0cf10000 0x0 0x1000>;
3399+
reg-names = "security", "gpio";
3400+
wakeup-parent = <&pmc>;
3401+
interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
3405+
gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
3409+
};
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};
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33523412
/* TOP_MMIO */
@@ -3802,6 +3862,34 @@
38023862
<0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */
38033863
<0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */
38043864

3865+
gpio_uphy: gpio@8300000 {
3866+
compatible = "nvidia,tegra264-gpio-uphy";
3867+
reg = <0x00 0x08300000 0x0 0x2000>,
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<0x00 0x08310000 0x0 0x2000>;
3869+
reg-names = "security", "gpio";
3870+
wakeup-parent = <&pmc>;
3871+
interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3873+
<GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3874+
<GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
3875+
<GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
3876+
<GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
3877+
<GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
3878+
<GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
3879+
<GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
3880+
<GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
3881+
<GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
3882+
<GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
3883+
<GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
3884+
<GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
3885+
<GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
3886+
<GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
3887+
gpio-controller;
3888+
#gpio-cells = <2>;
3889+
interrupt-controller;
3890+
#interrupt-cells = <2>;
3891+
};
3892+
38053893
pci@8400000 {
38063894
compatible = "nvidia,tegra264-pcie";
38073895
reg = <0xa8 0xb0000000 0x0 0x10000000>,

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