Merge tag 'memory-controller-drv-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v7.1

1. TegraMC:
 - Few fixes for older issues - missing clock on Tegra264,
   missing enabling of DLL for Tegra30 and Tegra124.
 - Simplify the code in a few places.
 - Rework handling interrupts on different variants and add support for
   error logging on Tegra 264.

2. Drop Baikal SoC bt1-l2-ctl driver, because SoC support is being
   removed tree-wide.

* tag 'memory-controller-drv-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra: Add MC error logging support for Tegra264
  memory: tegra: Prepare for supporting multiple intmask registers
  memory: tegra: Group SoC specific fields
  memory: tegra: Add support for multiple IRQs
  memory: tegra: Group register and fields
  memory: tegra: Group error handling related registers
  memory: tegra-mc: Use %pe format
  memory: tegra-mc: Simplify printing PTR_ERR with dev_err_probe
  memory: tegra-mc: Drop tegra_mc_setup_latency_allowance() return value
  memory: renesas-rpc-if: Simplify printing PTR_ERR with dev_err_probe
  memory: brcmstb_memc: Expand LPDDR4 check to cover for LPDDR5
  dt-bindings: cache: bt1-l2-ctl: Remove unused bindings
  memory: bt1-l2-ctl: Remove not-going-to-be-supported code for Baikal SoC
  memory: tegra30-emc: Fix dll_change check
  memory: tegra124-emc: Fix dll_change check
  memory: tegra: Add support for DBB clock on Tegra264

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Author: arndb

Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml

@@ -64,17 +64,6 @@ config BRCMSTB_MEMC
 	  controller and specifically control the Self Refresh Power Down
 	  (SRPD) inactivity timeout.
 
-config BT1_L2_CTL
-	bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
-	depends on MIPS_BAIKAL_T1 || COMPILE_TEST
-	select MFD_SYSCON
-	help
-	  Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
-	  resides Coherency Manager v2 with embedded 1MB L2-cache. It's
-	  possible to tune the L2 cache performance up by setting the data,
-	  tags and way-select latencies of RAM access. This driver provides a
-	  dt properties-based and sysfs interface for it.
-
 config TI_AEMIF
 	tristate "Texas Instruments AEMIF driver"
 	depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST

drivers/memory/Kconfig

@@ -11,7 +11,6 @@ obj-$(CONFIG_ARM_PL172_MPMC)	+= pl172.o
 obj-$(CONFIG_ATMEL_EBI)		+= atmel-ebi.o
 obj-$(CONFIG_BRCMSTB_DPFE)	+= brcmstb_dpfe.o
 obj-$(CONFIG_BRCMSTB_MEMC)	+= brcmstb_memc.o
-obj-$(CONFIG_BT1_L2_CTL)	+= bt1-l2-ctl.o
 obj-$(CONFIG_TI_AEMIF)		+= ti-aemif.o
 obj-$(CONFIG_TI_EMIF)		+= emif.o
 obj-$(CONFIG_OMAP_GPMC)		+= omap-gpmc.o

drivers/memory/Makefile

@@ -14,6 +14,7 @@
 
 #define REG_MEMC_CNTRLR_CONFIG		0x00
 #define  CNTRLR_CONFIG_LPDDR4_SHIFT	5
+#define  CNTRLR_CONFIG_LPDDR5_SHIFT	6
 #define  CNTRLR_CONFIG_MASK		0xf
 #define REG_MEMC_SRPD_CFG_21		0x20
 #define REG_MEMC_SRPD_CFG_20		0x34
@@ -34,14 +35,15 @@ struct brcmstb_memc {
 	u32 srpd_offset;
 };
 
-static int brcmstb_memc_uses_lpddr4(struct brcmstb_memc *memc)
+static int brcmstb_memc_uses_lpddr45(struct brcmstb_memc *memc)
 {
 	void __iomem *config = memc->ddr_ctrl + REG_MEMC_CNTRLR_CONFIG;
 	u32 reg;
 
 	reg = readl_relaxed(config) & CNTRLR_CONFIG_MASK;
 
-	return reg == CNTRLR_CONFIG_LPDDR4_SHIFT;
+	return reg == CNTRLR_CONFIG_LPDDR4_SHIFT ||
+	       reg == CNTRLR_CONFIG_LPDDR5_SHIFT;
 }
 
 static int brcmstb_memc_srpd_config(struct brcmstb_memc *memc,
@@ -95,7 +97,7 @@ static ssize_t srpd_store(struct device *dev, struct device_attribute *attr,
 	 * dynamic tuning process will also get affected by the inactivity
 	 * timeout, thus making it non functional.
 	 */
-	if (brcmstb_memc_uses_lpddr4(memc))
+	if (brcmstb_memc_uses_lpddr45(memc))
 		return -EOPNOTSUPP;
 
 	ret = kstrtouint(buf, 10, &val);