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Kuppuswamy Sathyanarayananrafaeljw
Kuppuswamy Sathyanarayanan
authored and
rafaeljw
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powercap: intel_rapl: Consolidate PL4 and PMU support flags into rapl_defaults
Currently, PL4 and MSR-based RAPL PMU support are detected using separate CPU ID tables (pl4_support_ids and pmu_support_ids) in the MSR driver probe path. This creates a maintenance burden since adding a new CPU requires updates in two places: the rapl_ids table and one or both of these capability tables. Consolidate PL4 and PMU capability information directly into struct rapl_defaults by adding msr_pl4_support and msr_pmu_support flags. This allows per-CPU capability to be expressed in a single place alongside other per-CPU defaults, eliminating the duplicate CPU ID tables entirely. No functional changes are intended. Co-developed-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: https://patch.msgid.link/20260331211950.3329932-8-sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1 parent b0ee511 commit c3bb8d4

2 files changed

Lines changed: 38 additions & 47 deletions

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‎drivers/powercap/intel_rapl_msr.c‎

Lines changed: 36 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -216,33 +216,6 @@ static int rapl_msr_write_raw(int cpu, struct reg_action *ra)
216216
return ra->err;
217217
}
218218

219-
/* List of verified CPUs. */
220-
static const struct x86_cpu_id pl4_support_ids[] = {
221-
X86_MATCH_VFM(INTEL_ICELAKE_L, NULL),
222-
X86_MATCH_VFM(INTEL_TIGERLAKE_L, NULL),
223-
X86_MATCH_VFM(INTEL_ALDERLAKE, NULL),
224-
X86_MATCH_VFM(INTEL_ALDERLAKE_L, NULL),
225-
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, NULL),
226-
X86_MATCH_VFM(INTEL_RAPTORLAKE, NULL),
227-
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, NULL),
228-
X86_MATCH_VFM(INTEL_METEORLAKE, NULL),
229-
X86_MATCH_VFM(INTEL_METEORLAKE_L, NULL),
230-
X86_MATCH_VFM(INTEL_ARROWLAKE_U, NULL),
231-
X86_MATCH_VFM(INTEL_ARROWLAKE_H, NULL),
232-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
233-
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
234-
X86_MATCH_VFM(INTEL_NOVALAKE, NULL),
235-
X86_MATCH_VFM(INTEL_NOVALAKE_L, NULL),
236-
{}
237-
};
238-
239-
/* List of MSR-based RAPL PMU support CPUs */
240-
static const struct x86_cpu_id pmu_support_ids[] = {
241-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, NULL),
242-
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, NULL),
243-
{}
244-
};
245-
246219
static int rapl_check_unit_atom(struct rapl_domain *rd)
247220
{
248221
struct reg_action ra;
@@ -420,6 +393,23 @@ static const struct rapl_defaults rapl_defaults_amd = {
420393
.check_unit = rapl_default_check_unit,
421394
};
422395

396+
static const struct rapl_defaults rapl_defaults_core_pl4 = {
397+
.floor_freq_reg_addr = 0,
398+
.check_unit = rapl_default_check_unit,
399+
.set_floor_freq = rapl_default_set_floor_freq,
400+
.compute_time_window = rapl_default_compute_time_window,
401+
.msr_pl4_support = 1,
402+
};
403+
404+
static const struct rapl_defaults rapl_defaults_core_pl4_pmu = {
405+
.floor_freq_reg_addr = 0,
406+
.check_unit = rapl_default_check_unit,
407+
.set_floor_freq = rapl_default_set_floor_freq,
408+
.compute_time_window = rapl_default_compute_time_window,
409+
.msr_pl4_support = 1,
410+
.msr_pmu_support = 1,
411+
};
412+
423413
static const struct x86_cpu_id rapl_ids[] = {
424414
X86_MATCH_VFM(INTEL_SANDYBRIDGE, &rapl_defaults_core),
425415
X86_MATCH_VFM(INTEL_SANDYBRIDGE_X, &rapl_defaults_core),
@@ -443,35 +433,35 @@ static const struct x86_cpu_id rapl_ids[] = {
443433
X86_MATCH_VFM(INTEL_KABYLAKE_L, &rapl_defaults_core),
444434
X86_MATCH_VFM(INTEL_KABYLAKE, &rapl_defaults_core),
445435
X86_MATCH_VFM(INTEL_CANNONLAKE_L, &rapl_defaults_core),
446-
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core),
436+
X86_MATCH_VFM(INTEL_ICELAKE_L, &rapl_defaults_core_pl4),
447437
X86_MATCH_VFM(INTEL_ICELAKE, &rapl_defaults_core),
448438
X86_MATCH_VFM(INTEL_ICELAKE_NNPI, &rapl_defaults_core),
449439
X86_MATCH_VFM(INTEL_ICELAKE_X, &rapl_defaults_hsw_server),
450440
X86_MATCH_VFM(INTEL_ICELAKE_D, &rapl_defaults_hsw_server),
451441
X86_MATCH_VFM(INTEL_COMETLAKE_L, &rapl_defaults_core),
452442
X86_MATCH_VFM(INTEL_COMETLAKE, &rapl_defaults_core),
453-
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core),
443+
X86_MATCH_VFM(INTEL_TIGERLAKE_L, &rapl_defaults_core_pl4),
454444
X86_MATCH_VFM(INTEL_TIGERLAKE, &rapl_defaults_core),
455445
X86_MATCH_VFM(INTEL_ROCKETLAKE, &rapl_defaults_core),
456-
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core),
457-
X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core),
458-
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core),
459-
X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core),
460-
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core),
446+
X86_MATCH_VFM(INTEL_ALDERLAKE, &rapl_defaults_core_pl4),
447+
X86_MATCH_VFM(INTEL_ALDERLAKE_L, &rapl_defaults_core_pl4),
448+
X86_MATCH_VFM(INTEL_ATOM_GRACEMONT, &rapl_defaults_core_pl4),
449+
X86_MATCH_VFM(INTEL_RAPTORLAKE, &rapl_defaults_core_pl4),
450+
X86_MATCH_VFM(INTEL_RAPTORLAKE_P, &rapl_defaults_core_pl4),
461451
X86_MATCH_VFM(INTEL_RAPTORLAKE_S, &rapl_defaults_core),
462452
X86_MATCH_VFM(INTEL_BARTLETTLAKE, &rapl_defaults_core),
463-
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core),
464-
X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core),
453+
X86_MATCH_VFM(INTEL_METEORLAKE, &rapl_defaults_core_pl4),
454+
X86_MATCH_VFM(INTEL_METEORLAKE_L, &rapl_defaults_core_pl4),
465455
X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &rapl_defaults_spr_server),
466456
X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &rapl_defaults_spr_server),
467457
X86_MATCH_VFM(INTEL_LUNARLAKE_M, &rapl_defaults_core),
468-
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core),
469-
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core),
470-
X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core),
471-
X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core),
472-
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core),
458+
X86_MATCH_VFM(INTEL_PANTHERLAKE_L, &rapl_defaults_core_pl4_pmu),
459+
X86_MATCH_VFM(INTEL_WILDCATLAKE_L, &rapl_defaults_core_pl4_pmu),
460+
X86_MATCH_VFM(INTEL_NOVALAKE, &rapl_defaults_core_pl4),
461+
X86_MATCH_VFM(INTEL_NOVALAKE_L, &rapl_defaults_core_pl4),
462+
X86_MATCH_VFM(INTEL_ARROWLAKE_H, &rapl_defaults_core_pl4),
473463
X86_MATCH_VFM(INTEL_ARROWLAKE, &rapl_defaults_core),
474-
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core),
464+
X86_MATCH_VFM(INTEL_ARROWLAKE_U, &rapl_defaults_core_pl4),
475465
X86_MATCH_VFM(INTEL_LAKEFIELD, &rapl_defaults_core),
476466

477467
X86_MATCH_VFM(INTEL_ATOM_SILVERMONT, &rapl_defaults_byt),
@@ -498,7 +488,6 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
498488

499489
static int rapl_msr_probe(struct platform_device *pdev)
500490
{
501-
const struct x86_cpu_id *id = x86_match_cpu(pl4_support_ids);
502491
int ret;
503492

504493
switch (boot_cpu_data.x86_vendor) {
@@ -518,16 +507,16 @@ static int rapl_msr_probe(struct platform_device *pdev)
518507
rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
519508
rapl_msr_priv->rpi = rpi_msr;
520509

521-
if (id) {
510+
if (rapl_msr_priv->defaults->msr_pl4_support) {
522511
rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);
523512
rapl_msr_priv->regs[RAPL_DOMAIN_PACKAGE][RAPL_DOMAIN_REG_PL4].msr =
524513
MSR_VR_CURRENT_CONFIG;
525-
pr_info("PL4 support detected.\n");
514+
pr_info("PL4 support detected (updated).\n");
526515
}
527516

528-
if (x86_match_cpu(pmu_support_ids)) {
517+
if (rapl_msr_priv->defaults->msr_pmu_support) {
529518
rapl_msr_pmu = true;
530-
pr_info("MSR-based RAPL PMU support enabled\n");
519+
pr_info("MSR-based RAPL PMU support enabled (updated)\n");
531520
}
532521

533522
rapl_msr_priv->control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);

‎include/linux/intel_rapl.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,8 @@ struct rapl_defaults {
135135
unsigned int dram_domain_energy_unit;
136136
unsigned int psys_domain_energy_unit;
137137
bool spr_psys_bits;
138+
bool msr_pl4_support;
139+
bool msr_pmu_support;
138140
};
139141

140142
#define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \

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