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Kuppuswamy Sathyanarayananrafaeljw
Kuppuswamy Sathyanarayanan
authored and
rafaeljw
committed
powercap: intel_rapl: Move MSR primitives to MSR driver
MSR-specific RAPL primitives differ from those used by TPMI and MMIO interfaces. Keeping them in the common driver requires interface-specific handling logic and makes the common layer unnecessarily complex. Move the MSR primitive definitions and associated bitmasks into the MSR interface driver. This change includes: 1. Move MSR-specific bitmask definitions to RAPL MSR driver. 2. Add MSR-local struct rapl_primitive_info instance and assign it to priv->rpi during MSR probe. 3. Remove the primitive assignment logic from rapl_config() in the common driver. No functional changes are intended. Co-developed-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: https://patch.msgid.link/20260331211950.3329932-7-sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1 parent d7a718f commit b0ee511

2 files changed

Lines changed: 99 additions & 105 deletions

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‎drivers/powercap/intel_rapl_common.c‎

Lines changed: 0 additions & 105 deletions
Original file line numberDiff line numberDiff line change
@@ -30,24 +30,8 @@
3030
#include <asm/intel-family.h>
3131
#include <asm/msr.h>
3232

33-
/* bitmasks for RAPL MSRs, used by primitive access functions */
3433
#define ENERGY_STATUS_MASK GENMASK(31, 0)
3534

36-
#define POWER_LIMIT1_MASK GENMASK(14, 0)
37-
#define POWER_LIMIT1_ENABLE BIT(15)
38-
#define POWER_LIMIT1_CLAMP BIT(16)
39-
40-
#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
41-
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
42-
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
43-
#define POWER_HIGH_LOCK BIT_ULL(63)
44-
#define POWER_LOW_LOCK BIT(31)
45-
46-
#define POWER_LIMIT4_MASK GENMASK(12, 0)
47-
48-
#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
49-
#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
50-
5135
#define POWER_UNIT_OFFSET 0x00
5236
#define POWER_UNIT_MASK GENMASK(3, 0)
5337

@@ -57,28 +41,6 @@
5741
#define TIME_UNIT_OFFSET 0x10
5842
#define TIME_UNIT_MASK GENMASK(19, 16)
5943

60-
#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
61-
#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
62-
#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
63-
#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
64-
65-
#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
66-
#define PP_POLICY_MASK GENMASK(4, 0)
67-
68-
/*
69-
* SPR has different layout for Psys Domain PowerLimit registers.
70-
* There are 17 bits of PL1 and PL2 instead of 15 bits.
71-
* The Enable bits and TimeWindow bits are also shifted as a result.
72-
*/
73-
#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
74-
#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
75-
76-
#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
77-
#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
78-
79-
#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
80-
#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
81-
8244
/* Non HW constants */
8345
#define RAPL_PRIMITIVE_DUMMY BIT(2)
8446

@@ -598,64 +560,6 @@ static u64 rapl_unit_xlate(struct rapl_domain *rd, enum unit_type type,
598560
return div64_u64(value, scale);
599561
}
600562

601-
/* RAPL primitives for MSR and MMIO I/F */
602-
static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
603-
/* name, mask, shift, msr index, unit divisor */
604-
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
605-
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
606-
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
607-
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
608-
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
609-
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
610-
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
611-
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
612-
[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
613-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
614-
[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
615-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
616-
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
617-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
618-
[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
619-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
620-
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
621-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
622-
[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
623-
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
624-
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
625-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
626-
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
627-
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
628-
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
629-
POWER_INFO_THERMAL_SPEC_MASK, 0,
630-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
631-
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
632-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
633-
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
634-
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
635-
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
636-
POWER_INFO_MAX_TIME_WIN_MASK, 48,
637-
RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
638-
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
639-
PERF_STATUS_THROTTLE_TIME_MASK, 0,
640-
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
641-
[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
642-
RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
643-
[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
644-
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
645-
[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
646-
32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
647-
[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
648-
17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
649-
0),
650-
[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
651-
49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
652-
0),
653-
[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
654-
19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
655-
[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
656-
51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
657-
};
658-
659563
static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
660564
{
661565
struct rapl_primitive_info *rpi = rp->priv->rpi;
@@ -668,15 +572,6 @@ static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
668572

669573
static int rapl_config(struct rapl_package *rp)
670574
{
671-
switch (rp->priv->type) {
672-
/* MMIO I/F shares the same register layout as MSR registers */
673-
case RAPL_IF_MSR:
674-
rp->priv->rpi = rpi_msr;
675-
break;
676-
default:
677-
return -EINVAL;
678-
}
679-
680575
/* defaults_msr can be NULL on unsupported platforms */
681576
if (!rp->priv->defaults || !rp->priv->rpi)
682577
return -ENODEV;

‎drivers/powercap/intel_rapl_msr.c‎

Lines changed: 99 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,46 @@
4444
#define TIME_UNIT_OFFSET 0x10
4545
#define TIME_UNIT_MASK GENMASK(19, 16)
4646

47+
/* bitmasks for RAPL MSRs, used by primitive access functions */
48+
#define ENERGY_STATUS_MASK GENMASK(31, 0)
49+
50+
#define POWER_LIMIT1_MASK GENMASK(14, 0)
51+
#define POWER_LIMIT1_ENABLE BIT(15)
52+
#define POWER_LIMIT1_CLAMP BIT(16)
53+
54+
#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
55+
#define POWER_LIMIT2_ENABLE BIT_ULL(47)
56+
#define POWER_LIMIT2_CLAMP BIT_ULL(48)
57+
#define POWER_HIGH_LOCK BIT_ULL(63)
58+
#define POWER_LOW_LOCK BIT(31)
59+
60+
#define POWER_LIMIT4_MASK GENMASK(12, 0)
61+
62+
#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
63+
#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
64+
65+
#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
66+
#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
67+
#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
68+
#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
69+
70+
#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
71+
#define PP_POLICY_MASK GENMASK(4, 0)
72+
73+
/*
74+
* SPR has different layout for Psys Domain PowerLimit registers.
75+
* There are 17 bits of PL1 and PL2 instead of 15 bits.
76+
* The Enable bits and TimeWindow bits are also shifted as a result.
77+
*/
78+
#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
79+
#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
80+
81+
#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
82+
#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
83+
84+
#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
85+
#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
86+
4787
/* Sideband MBI registers */
4888
#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
4989
#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
@@ -268,6 +308,64 @@ static u64 rapl_compute_time_window_atom(struct rapl_domain *rd, u64 value,
268308
return value ? value * rd->time_unit : rd->time_unit;
269309
}
270310

311+
/* RAPL primitives for MSR I/F */
312+
static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
313+
/* name, mask, shift, msr index, unit divisor */
314+
[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
315+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
316+
[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
317+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
318+
[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
319+
RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
320+
[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
321+
RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
322+
[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
323+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
324+
[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
325+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
326+
[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
327+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
328+
[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
329+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
330+
[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
331+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
332+
[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
333+
RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
334+
[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
335+
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
336+
[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
337+
RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
338+
[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
339+
POWER_INFO_THERMAL_SPEC_MASK, 0,
340+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
341+
[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
342+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
343+
[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
344+
RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
345+
[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
346+
POWER_INFO_MAX_TIME_WIN_MASK, 48,
347+
RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
348+
[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
349+
PERF_STATUS_THROTTLE_TIME_MASK, 0,
350+
RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
351+
[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
352+
RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
353+
[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
354+
RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
355+
[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
356+
32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
357+
[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
358+
17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
359+
0),
360+
[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
361+
49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
362+
0),
363+
[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
364+
19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
365+
[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
366+
51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
367+
};
368+
271369
static const struct rapl_defaults rapl_defaults_core = {
272370
.floor_freq_reg_addr = 0,
273371
.check_unit = rapl_default_check_unit,
@@ -418,6 +516,7 @@ static int rapl_msr_probe(struct platform_device *pdev)
418516
rapl_msr_priv->read_raw = rapl_msr_read_raw;
419517
rapl_msr_priv->write_raw = rapl_msr_write_raw;
420518
rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
519+
rapl_msr_priv->rpi = rpi_msr;
421520

422521
if (id) {
423522
rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);

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