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bebarinobebarino
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Merge tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull more Renesas clk driver updates from Geert Uytterhoeven: - Add SPI clocks and resets on Renesas RZ/G3E - Add PCIe clocks and resets on Renesas RZ/V2N, RZ/V2H(P), and RZ/G3E - Enable watchdog reset on Renesas RZ/N1D - Remove clocks for watchdogs meant for other CPU cores on Renesas RZ/V2N - Handle critical clock during system resume on Renesas RZ/G2L, RZ/G2UL, and RZ/G3S - Add initial support for the Renesas RZ/G3L (R9A08G046) SoC * tag 'renesas-clk-for-v7.1-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: Add support for RZ/G3L SoC dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC clk: renesas: rzg2l: Re-enable critical module clocks during resume clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper() clk: renesas: rzg2l: Add helper for mod clock enable/disable clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries clk: renesas: rzg2l: Add support for critical resets clk: renesas: r9a09g056: Remove entries for WDT{0,2,3} clk: renesas: r9a06g032: Enable watchdog reset sources clk: renesas: cpg-mssr: Use struct_size() helper clk: renesas: r9a09g047: Add PCIe clocks and reset clk: renesas: r9a09g057: Add PCIe clocks and reset clk: renesas: r9a09g056: Add PCIe clocks and reset clk: renesas: r9a09g047: Add entries for the RSPIs
2 parents 96df813 + 7789466 commit 98266d5

15 files changed

Lines changed: 698 additions & 38 deletions

File tree

‎Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml‎

Lines changed: 35 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,19 +28,30 @@ properties:
2828
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
2929
- renesas,r9a07g054-cpg # RZ/V2L
3030
- renesas,r9a08g045-cpg # RZ/G3S
31+
- renesas,r9a08g046-cpg # RZ/G3L
3132
- renesas,r9a09g011-cpg # RZ/V2M
3233

3334
reg:
3435
maxItems: 1
3536

3637
clocks:
37-
maxItems: 1
38+
minItems: 1
39+
items:
40+
- description: Clock source to CPG can be either from external clock
41+
input (EXCLK) or crystal oscillator (XIN/XOUT).
42+
- description: ETH0 TXC clock input
43+
- description: ETH0 RXC clock input
44+
- description: ETH1 TXC clock input
45+
- description: ETH1 RXC clock input
3846

3947
clock-names:
40-
description:
41-
Clock source to CPG can be either from external clock input (EXCLK) or
42-
crystal oscillator (XIN/XOUT).
43-
const: extal
48+
minItems: 1
49+
items:
50+
- const: extal
51+
- const: eth0_txc_tx_clk
52+
- const: eth0_rxc_rx_clk
53+
- const: eth1_txc_tx_clk
54+
- const: eth1_rxc_rx_clk
4455

4556
'#clock-cells':
4657
description: |
@@ -74,6 +85,25 @@ required:
7485
- '#power-domain-cells'
7586
- '#reset-cells'
7687

88+
allOf:
89+
- if:
90+
properties:
91+
compatible:
92+
contains:
93+
const: renesas,r9a08g046-cpg
94+
then:
95+
properties:
96+
clocks:
97+
minItems: 5
98+
clock-names:
99+
minItems: 5
100+
else:
101+
properties:
102+
clocks:
103+
maxItems: 1
104+
clock-names:
105+
maxItems: 1
106+
77107
additionalProperties: false
78108

79109
examples:

‎drivers/clk/renesas/Kconfig‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ config CLK_RENESAS
3939
select CLK_R9A07G044 if ARCH_R9A07G044
4040
select CLK_R9A07G054 if ARCH_R9A07G054
4141
select CLK_R9A08G045 if ARCH_R9A08G045
42+
select CLK_R9A08G046 if ARCH_R9A08G046
4243
select CLK_R9A09G011 if ARCH_R9A09G011
4344
select CLK_R9A09G047 if ARCH_R9A09G047
4445
select CLK_R9A09G056 if ARCH_R9A09G056
@@ -194,6 +195,10 @@ config CLK_R9A08G045
194195
bool "RZ/G3S clock support" if COMPILE_TEST
195196
select CLK_RZG2L
196197

198+
config CLK_R9A08G046
199+
bool "RZ/G3L clock support" if COMPILE_TEST
200+
select CLK_RZG2L
201+
197202
config CLK_R9A09G011
198203
bool "RZ/V2M clock support" if COMPILE_TEST
199204
select CLK_RZG2L
@@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
250255
This is a driver for R-Car USB2 clock selector
251256

252257
config CLK_RZG2L
253-
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
258+
bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
254259
select RESET_CONTROLLER
255260

256261
config CLK_RZV2H

‎drivers/clk/renesas/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
3636
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
3737
obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
3838
obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
39+
obj-$(CONFIG_CLK_R9A08G046) += r9a08g046-cpg.o
3940
obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
4041
obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
4142
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o

‎drivers/clk/renesas/r9a06g032-clocks.c‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1342,8 +1342,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev)
13421342
/* Clear potentially pending resets */
13431343
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1,
13441344
clocks->reg + R9A06G032_SYSCTRL_RSTCTRL);
1345-
/* Allow software reset */
1346-
writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
1345+
/* Allow watchdog and software resets */
1346+
writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 |
1347+
R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN,
13471348
clocks->reg + R9A06G032_SYSCTRL_RSTEN);
13481349

13491350
error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,

‎drivers/clk/renesas/r9a07g043-cpg.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -379,6 +379,11 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
379379
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
380380
};
381381

382+
static const unsigned int r9a07g043_crit_resets[] = {
383+
R9A07G043_DMAC_ARESETN,
384+
R9A07G043_DMAC_RST_ASYNC,
385+
};
386+
382387
#ifdef CONFIG_ARM64
383388
static const unsigned int r9a07g043_no_pm_mod_clks[] = {
384389
MOD_CLK_BASE + R9A07G043_CRU_SYSCLK,
@@ -420,5 +425,9 @@ const struct rzg2l_cpg_info r9a07g043_cpg_info = {
420425
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
421426
#endif
422427

428+
/* Critical Resets */
429+
.crit_resets = r9a07g043_crit_resets,
430+
.num_crit_resets = ARRAY_SIZE(r9a07g043_crit_resets),
431+
423432
.has_clk_mon_regs = true,
424433
};

‎drivers/clk/renesas/r9a07g044-cpg.c‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -489,6 +489,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
489489
MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
490490
};
491491

492+
static const unsigned int r9a07g044_crit_resets[] = {
493+
R9A07G044_DMAC_ARESETN,
494+
R9A07G044_DMAC_RST_ASYNC,
495+
};
496+
492497
static const unsigned int r9a07g044_no_pm_mod_clks[] = {
493498
MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,
494499
MOD_CLK_BASE + R9A07G044_CRU_VCLK,
@@ -519,6 +524,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = {
519524
.resets = r9a07g044_resets,
520525
.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
521526

527+
/* Critical Resets */
528+
.crit_resets = r9a07g044_crit_resets,
529+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
530+
522531
.has_clk_mon_regs = true,
523532
};
524533
#endif
@@ -548,6 +557,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = {
548557
.resets = r9a07g044_resets,
549558
.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */
550559

560+
/* Critical Resets */
561+
.crit_resets = r9a07g044_crit_resets,
562+
.num_crit_resets = ARRAY_SIZE(r9a07g044_crit_resets),
563+
551564
.has_clk_mon_regs = true,
552565
};
553566
#endif

‎drivers/clk/renesas/r9a08g045-cpg.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -361,6 +361,11 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
361361
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
362362
};
363363

364+
static const unsigned int r9a08g045_crit_resets[] = {
365+
R9A08G045_DMAC_ARESETN,
366+
R9A08G045_DMAC_RST_ASYNC,
367+
};
368+
364369
static const unsigned int r9a08g045_no_pm_mod_clks[] = {
365370
MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM,
366371
};
@@ -389,5 +394,9 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info = {
389394
.resets = r9a08g045_resets,
390395
.num_resets = R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */
391396

397+
/* Critical Resets */
398+
.crit_resets = r9a08g045_crit_resets,
399+
.num_crit_resets = ARRAY_SIZE(r9a08g045_crit_resets),
400+
392401
.has_clk_mon_regs = true,
393402
};

‎drivers/clk/renesas/r9a08g046-cpg.c‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,153 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* RZ/G3L CPG driver
4+
*
5+
* Copyright (C) 2026 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
14+
15+
#include "rzg2l-cpg.h"
16+
17+
/* RZ/G3L Specific registers. */
18+
#define G3L_CPG_PL2_DDIV (0x204)
19+
#define G3L_CPG_PL3_DDIV (0x208)
20+
#define G3L_CLKDIVSTATUS (0x280)
21+
22+
/* RZ/G3L Specific division configuration. */
23+
#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
24+
#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
25+
#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
26+
27+
/* RZ/G3L Clock status configuration. */
28+
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
29+
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
30+
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
31+
32+
enum clk_ids {
33+
/* Core Clock Outputs exported to DT */
34+
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
35+
36+
/* External Input Clocks */
37+
CLK_EXTAL,
38+
CLK_ETH0_TXC_TX_CLK_IN,
39+
CLK_ETH0_RXC_RX_CLK_IN,
40+
CLK_ETH1_TXC_TX_CLK_IN,
41+
CLK_ETH1_RXC_RX_CLK_IN,
42+
43+
/* Internal Core Clocks */
44+
CLK_PLL2,
45+
CLK_PLL2_DIV2,
46+
CLK_PLL3,
47+
CLK_PLL3_DIV2,
48+
49+
/* Module Clocks */
50+
MOD_CLK_BASE,
51+
};
52+
53+
/* Divider tables */
54+
static const struct clk_div_table dtable_4_128[] = {
55+
{ 0, 4 },
56+
{ 1, 8 },
57+
{ 2, 16 },
58+
{ 3, 128 },
59+
{ 0, 0 },
60+
};
61+
62+
static const struct clk_div_table dtable_8_256[] = {
63+
{ 0, 8 },
64+
{ 1, 16 },
65+
{ 2, 32 },
66+
{ 3, 256 },
67+
{ 0, 0 },
68+
};
69+
70+
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
71+
/* External Clock Inputs */
72+
DEF_INPUT("extal", CLK_EXTAL),
73+
DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
74+
DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
75+
DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
76+
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
77+
78+
/* Internal Core Clocks */
79+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
80+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
81+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
82+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
83+
84+
/* Core output clk */
85+
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
86+
dtable_8_256, 0, 0, 0, NULL),
87+
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
88+
dtable_4_128, 0, 0, 0, NULL),
89+
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
90+
dtable_4_128, 0, 0, 0, NULL),
91+
};
92+
93+
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
94+
DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
95+
MSTOP(BUS_PERI_COM, BIT(12))),
96+
DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
97+
MSTOP(BUS_PERI_CPU, BIT(13))),
98+
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
99+
MSTOP(BUS_PERI_CPU, BIT(13))),
100+
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
101+
MSTOP(BUS_REG1, BIT(2))),
102+
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
103+
MSTOP(BUS_REG1, BIT(3))),
104+
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
105+
MSTOP(BUS_MCPU2, BIT(1))),
106+
};
107+
108+
static const struct rzg2l_reset r9a08g046_resets[] = {
109+
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
110+
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
111+
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
112+
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
113+
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
114+
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
115+
};
116+
117+
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
118+
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
119+
MOD_CLK_BASE + R9A08G046_IA55_CLK,
120+
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
121+
};
122+
123+
static const unsigned int r9a08g046_crit_resets[] = {
124+
R9A08G046_DMAC_ARESETN,
125+
R9A08G046_DMAC_RST_ASYNC,
126+
};
127+
128+
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
129+
/* Core Clocks */
130+
.core_clks = r9a08g046_core_clks,
131+
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
132+
.last_dt_core_clk = LAST_DT_CORE_CLK,
133+
.num_total_core_clks = MOD_CLK_BASE,
134+
135+
/* Critical Module Clocks */
136+
.crit_mod_clks = r9a08g046_crit_mod_clks,
137+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
138+
139+
/* Module Clocks */
140+
.mod_clks = r9a08g046_mod_clks,
141+
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
142+
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
143+
144+
/* Resets */
145+
.resets = r9a08g046_resets,
146+
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
147+
148+
/* Critical Resets */
149+
.crit_resets = r9a08g046_crit_resets,
150+
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
151+
152+
.has_clk_mon_regs = true,
153+
};

‎drivers/clk/renesas/r9a09g047-cpg.c‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -224,6 +224,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
224224
BUS_MSTOP(5, BIT(13))),
225225
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
226226
BUS_MSTOP(5, BIT(13))),
227+
DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
228+
BUS_MSTOP(11, BIT(0))),
229+
DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
230+
BUS_MSTOP(11, BIT(0))),
231+
DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
232+
BUS_MSTOP(11, BIT(0))),
233+
DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
234+
BUS_MSTOP(11, BIT(1))),
235+
DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
236+
BUS_MSTOP(11, BIT(1))),
237+
DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
238+
BUS_MSTOP(11, BIT(1))),
239+
DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
240+
BUS_MSTOP(11, BIT(2))),
241+
DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
242+
BUS_MSTOP(11, BIT(2))),
243+
DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
244+
BUS_MSTOP(11, BIT(2))),
227245
DEF_MOD("rsci0_pclk", CLK_PLLCLN_DIV16, 5, 13, 2, 29,
228246
BUS_MSTOP(11, BIT(3))),
229247
DEF_MOD("rsci0_tclk", CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -424,6 +442,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
424442
BUS_MSTOP(8, BIT(6))),
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DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3,
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BUS_MSTOP(8, BIT(6))),
445+
DEF_MOD("pcie_0_aclk", CLK_PLLDTY_ACPU_DIV2, 12, 4, 6, 4,
446+
BUS_MSTOP(1, BIT(15))),
447+
DEF_MOD("pcie_0_clk_pmu", CLK_PLLDTY_ACPU_DIV2, 12, 5, 6, 5,
448+
BUS_MSTOP(1, BIT(15))),
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DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18,
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BUS_MSTOP(9, BIT(4))),
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DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19,
@@ -457,6 +479,12 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
457479
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
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DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
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DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
482+
DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
483+
DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
484+
DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
485+
DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
486+
DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
487+
DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
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DEF_RST(8, 1, 3, 18), /* RSCI0_PRESETN */
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DEF_RST(8, 2, 3, 19), /* RSCI0_TRESETN */
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DEF_RST(8, 3, 3, 20), /* RSCI1_PRESETN */
@@ -503,6 +531,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */
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DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */
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DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */
534+
DEF_RST(11, 2, 5, 3), /* PCIE_0_ARESETN */
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DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
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DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
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DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */

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