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bijudasgeertu
bijudas
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geertu
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clk: renesas: Add support for RZ/G3L SoC
The clock structure for RZ/G3L is almost identical to that of the RZ/G3S SoC with more IP blocks such as LCDC, CRU, LVDS, and GPU. Add minimal clock and reset entries required to boot the system on Renesas RZ/G3L SMARC EVK and bind it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/20260324114329.268249-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
1 parent 30e7ff3 commit 7789466

5 files changed

Lines changed: 167 additions & 1 deletion

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‎drivers/clk/renesas/Kconfig‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ config CLK_RENESAS
3939
select CLK_R9A07G044 if ARCH_R9A07G044
4040
select CLK_R9A07G054 if ARCH_R9A07G054
4141
select CLK_R9A08G045 if ARCH_R9A08G045
42+
select CLK_R9A08G046 if ARCH_R9A08G046
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select CLK_R9A09G011 if ARCH_R9A09G011
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select CLK_R9A09G047 if ARCH_R9A09G047
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select CLK_R9A09G056 if ARCH_R9A09G056
@@ -194,6 +195,10 @@ config CLK_R9A08G045
194195
bool "RZ/G3S clock support" if COMPILE_TEST
195196
select CLK_RZG2L
196197

198+
config CLK_R9A08G046
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bool "RZ/G3L clock support" if COMPILE_TEST
200+
select CLK_RZG2L
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197202
config CLK_R9A09G011
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bool "RZ/V2M clock support" if COMPILE_TEST
199204
select CLK_RZG2L
@@ -250,7 +255,7 @@ config CLK_RCAR_USB2_CLOCK_SEL
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This is a driver for R-Car USB2 clock selector
251256

252257
config CLK_RZG2L
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bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
258+
bool "RZ/{G2{L,UL},G3{S,L},V2L} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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256261
config CLK_RZV2H

‎drivers/clk/renesas/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@ obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
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obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
39+
obj-$(CONFIG_CLK_R9A08G046) += r9a08g046-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
4142
obj-$(CONFIG_CLK_R9A09G056) += r9a09g056-cpg.o

‎drivers/clk/renesas/r9a08g046-cpg.c‎

Lines changed: 153 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,153 @@
1+
// SPDX-License-Identifier: GPL-2.0
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/*
3+
* RZ/G3L CPG driver
4+
*
5+
* Copyright (C) 2026 Renesas Electronics Corp.
6+
*/
7+
8+
#include <linux/clk-provider.h>
9+
#include <linux/device.h>
10+
#include <linux/init.h>
11+
#include <linux/kernel.h>
12+
13+
#include <dt-bindings/clock/renesas,r9a08g046-cpg.h>
14+
15+
#include "rzg2l-cpg.h"
16+
17+
/* RZ/G3L Specific registers. */
18+
#define G3L_CPG_PL2_DDIV (0x204)
19+
#define G3L_CPG_PL3_DDIV (0x208)
20+
#define G3L_CLKDIVSTATUS (0x280)
21+
22+
/* RZ/G3L Specific division configuration. */
23+
#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
24+
#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
25+
#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
26+
27+
/* RZ/G3L Clock status configuration. */
28+
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
29+
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
30+
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
31+
32+
enum clk_ids {
33+
/* Core Clock Outputs exported to DT */
34+
LAST_DT_CORE_CLK = R9A08G046_USB_SCLK,
35+
36+
/* External Input Clocks */
37+
CLK_EXTAL,
38+
CLK_ETH0_TXC_TX_CLK_IN,
39+
CLK_ETH0_RXC_RX_CLK_IN,
40+
CLK_ETH1_TXC_TX_CLK_IN,
41+
CLK_ETH1_RXC_RX_CLK_IN,
42+
43+
/* Internal Core Clocks */
44+
CLK_PLL2,
45+
CLK_PLL2_DIV2,
46+
CLK_PLL3,
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CLK_PLL3_DIV2,
48+
49+
/* Module Clocks */
50+
MOD_CLK_BASE,
51+
};
52+
53+
/* Divider tables */
54+
static const struct clk_div_table dtable_4_128[] = {
55+
{ 0, 4 },
56+
{ 1, 8 },
57+
{ 2, 16 },
58+
{ 3, 128 },
59+
{ 0, 0 },
60+
};
61+
62+
static const struct clk_div_table dtable_8_256[] = {
63+
{ 0, 8 },
64+
{ 1, 16 },
65+
{ 2, 32 },
66+
{ 3, 256 },
67+
{ 0, 0 },
68+
};
69+
70+
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
71+
/* External Clock Inputs */
72+
DEF_INPUT("extal", CLK_EXTAL),
73+
DEF_INPUT("eth0_txc_tx_clk", CLK_ETH0_TXC_TX_CLK_IN),
74+
DEF_INPUT("eth0_rxc_rx_clk", CLK_ETH0_RXC_RX_CLK_IN),
75+
DEF_INPUT("eth1_txc_tx_clk", CLK_ETH1_TXC_TX_CLK_IN),
76+
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
77+
78+
/* Internal Core Clocks */
79+
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
80+
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
81+
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
82+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
83+
84+
/* Core output clk */
85+
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
86+
dtable_8_256, 0, 0, 0, NULL),
87+
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
88+
dtable_4_128, 0, 0, 0, NULL),
89+
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
90+
dtable_4_128, 0, 0, 0, NULL),
91+
};
92+
93+
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
94+
DEF_MOD("gic_gicclk", R9A08G046_GIC600_GICCLK, R9A08G046_CLK_P1, 0x514, 0,
95+
MSTOP(BUS_PERI_COM, BIT(12))),
96+
DEF_MOD("ia55_pclk", R9A08G046_IA55_PCLK, R9A08G046_CLK_P0, 0x518, 0,
97+
MSTOP(BUS_PERI_CPU, BIT(13))),
98+
DEF_MOD("ia55_clk", R9A08G046_IA55_CLK, R9A08G046_CLK_P1, 0x518, 1,
99+
MSTOP(BUS_PERI_CPU, BIT(13))),
100+
DEF_MOD("dmac_aclk", R9A08G046_DMAC_ACLK, R9A08G046_CLK_P3, 0x52c, 0,
101+
MSTOP(BUS_REG1, BIT(2))),
102+
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
103+
MSTOP(BUS_REG1, BIT(3))),
104+
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
105+
MSTOP(BUS_MCPU2, BIT(1))),
106+
};
107+
108+
static const struct rzg2l_reset r9a08g046_resets[] = {
109+
DEF_RST(R9A08G046_GIC600_GICRESET_N, 0x814, 0),
110+
DEF_RST(R9A08G046_GIC600_DBG_GICRESET_N, 0x814, 1),
111+
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
112+
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
113+
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
114+
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
115+
};
116+
117+
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
118+
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
119+
MOD_CLK_BASE + R9A08G046_IA55_CLK,
120+
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
121+
};
122+
123+
static const unsigned int r9a08g046_crit_resets[] = {
124+
R9A08G046_DMAC_ARESETN,
125+
R9A08G046_DMAC_RST_ASYNC,
126+
};
127+
128+
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
129+
/* Core Clocks */
130+
.core_clks = r9a08g046_core_clks,
131+
.num_core_clks = ARRAY_SIZE(r9a08g046_core_clks),
132+
.last_dt_core_clk = LAST_DT_CORE_CLK,
133+
.num_total_core_clks = MOD_CLK_BASE,
134+
135+
/* Critical Module Clocks */
136+
.crit_mod_clks = r9a08g046_crit_mod_clks,
137+
.num_crit_mod_clks = ARRAY_SIZE(r9a08g046_crit_mod_clks),
138+
139+
/* Module Clocks */
140+
.mod_clks = r9a08g046_mod_clks,
141+
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
142+
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
143+
144+
/* Resets */
145+
.resets = r9a08g046_resets,
146+
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
147+
148+
/* Critical Resets */
149+
.crit_resets = r9a08g046_crit_resets,
150+
.num_crit_resets = ARRAY_SIZE(r9a08g046_crit_resets),
151+
152+
.has_clk_mon_regs = true,
153+
};

‎drivers/clk/renesas/rzg2l-cpg.c‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2152,6 +2152,12 @@ static const struct of_device_id rzg2l_cpg_match[] = {
21522152
.data = &r9a08g045_cpg_info,
21532153
},
21542154
#endif
2155+
#ifdef CONFIG_CLK_R9A08G046
2156+
{
2157+
.compatible = "renesas,r9a08g046-cpg",
2158+
.data = &r9a08g046_cpg_info,
2159+
},
2160+
#endif
21552161
#ifdef CONFIG_CLK_R9A09G011
21562162
{
21572163
.compatible = "renesas,r9a09g011-cpg",

‎drivers/clk/renesas/rzg2l-cpg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,7 @@ extern const struct rzg2l_cpg_info r9a07g043_cpg_info;
316316
extern const struct rzg2l_cpg_info r9a07g044_cpg_info;
317317
extern const struct rzg2l_cpg_info r9a07g054_cpg_info;
318318
extern const struct rzg2l_cpg_info r9a08g045_cpg_info;
319+
extern const struct rzg2l_cpg_info r9a08g046_cpg_info;
319320
extern const struct rzg2l_cpg_info r9a09g011_cpg_info;
320321

321322
int rzg2l_cpg_sd_clk_mux_notifier(struct notifier_block *nb, unsigned long event, void *data);

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