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drm/amdgpu: Add THM 15.0.0 headers
Add headers for THM 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/include/asic_reg/thm/thm_15_0_0_offset.h‎

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/*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _thm_15_0_0_OFFSET_HEADER
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#define _thm_15_0_0_OFFSET_HEADER
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// addressBlock: thm_thm_SmuThmDec
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// base address: 0x59800
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#define regTHM_TCON_CUR_TMP 0x0000
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#define regTHM_TCON_CUR_TMP_BASE_IDX 0
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#define regTHM_TCON_HTC 0x0001
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#define regTHM_TCON_HTC_BASE_IDX 0
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#define regTHM_TCON_THERM_TRIP 0x0002
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#define regTHM_TCON_THERM_TRIP_BASE_IDX 0
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#define regTHM_CTF_DELAY 0x0004
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#define regTHM_CTF_DELAY_BASE_IDX 0
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#define regTHM_GPIO_PROCHOT_CTRL 0x0005
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#define regTHM_GPIO_PROCHOT_CTRL_BASE_IDX 0
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#define regTHM_SW_TEMP 0x0006
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#define regTHM_SW_TEMP_BASE_IDX 0
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#define regCG_MULT_THERMAL_CTRL 0x0007
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#define regCG_MULT_THERMAL_CTRL_BASE_IDX 0
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#define regCG_MULT_THERMAL_STATUS 0x0008
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#define regCG_MULT_THERMAL_STATUS_BASE_IDX 0
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#define regCG_THERMAL_RANGE 0x0009
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#define regCG_THERMAL_RANGE_BASE_IDX 0
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#define regTHM_TCON_LOCAL2 0x000a
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#define regTHM_TCON_LOCAL2_BASE_IDX 0
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#define regTHM_TCON_LOCAL3 0x000b
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#define regTHM_TCON_LOCAL3_BASE_IDX 0
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#define regTHM_TCON_LOCAL4 0x000c
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#define regTHM_TCON_LOCAL4_BASE_IDX 0
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#define regTHM_TCON_LOCAL5 0x000d
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#define regTHM_TCON_LOCAL5_BASE_IDX 0
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#define regTHM_TCON_LOCAL6 0x000e
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#define regTHM_TCON_LOCAL6_BASE_IDX 0
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#define regTHM_TCON_LOCAL7 0x000f
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#define regTHM_TCON_LOCAL7_BASE_IDX 0
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#define regTHM_TCON_LOCAL8 0x0010
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#define regTHM_TCON_LOCAL8_BASE_IDX 0
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#define regTHM_TCON_LOCAL9 0x0011
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#define regTHM_TCON_LOCAL9_BASE_IDX 0
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#define regTHM_TCON_LOCAL10 0x0012
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#define regTHM_TCON_LOCAL10_BASE_IDX 0
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#define regTHM_TCON_LOCAL11 0x0013
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#define regTHM_TCON_LOCAL11_BASE_IDX 0
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#define regTHM_TCON_LOCAL12 0x0014
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#define regTHM_TCON_LOCAL12_BASE_IDX 0
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#define regTHM_TCON_LOCAL13 0x0015
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#define regTHM_TCON_LOCAL13_BASE_IDX 0
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#define regTHM_TCON_LOCAL14 0x0016
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#define regTHM_TCON_LOCAL14_BASE_IDX 0
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#define regTHM_TCON_LOCAL15 0x0017
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#define regTHM_TCON_LOCAL15_BASE_IDX 0
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#define regTHM_PWRMGT 0x001b
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#define regTHM_PWRMGT_BASE_IDX 0
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#define regTHM_DIE1_TEMP 0x001c
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#define regTHM_DIE1_TEMP_BASE_IDX 0
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#define regTHM_DIE2_TEMP 0x001d
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#define regTHM_DIE2_TEMP_BASE_IDX 0
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#define regTHM_DIE3_TEMP 0x001e
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#define regTHM_DIE3_TEMP_BASE_IDX 0
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#define regSMUSBI_SBIREGADDR 0x0124
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#define regSMUSBI_SBIREGADDR_BASE_IDX 0
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#define regSMUSBI_SBIREGDATA 0x0125
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#define regSMUSBI_SBIREGDATA_BASE_IDX 0
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#define regSMUSBI_ERRATA_STAT_REG 0x0129
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#define regSMUSBI_ERRATA_STAT_REG_BASE_IDX 0
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#define regSMUSBI_SBICTRL 0x012a
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#define regSMUSBI_SBICTRL_BASE_IDX 0
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#define regSMUSBI_CKNBIRESET 0x012b
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#define regSMUSBI_CKNBIRESET_BASE_IDX 0
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#define regSMUSBI_TIMING 0x012c
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#define regSMUSBI_TIMING_BASE_IDX 0
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#define regSMUSBI_HS_TIMING 0x012d
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#define regSMUSBI_HS_TIMING_BASE_IDX 0
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#define regSBTSI_REMOTE_TEMP 0x012e
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#define regSBTSI_REMOTE_TEMP_BASE_IDX 0
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#define regSBRMI_CONTROL 0x012f
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#define regSBRMI_CONTROL_BASE_IDX 0
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#define regSBRMI_COMMAND 0x0130
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#define regSBRMI_COMMAND_BASE_IDX 0
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#define regSBRMI_WRITE_DATA0 0x0132
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#define regSBRMI_WRITE_DATA0_BASE_IDX 0
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#define regSBRMI_WRITE_DATA1 0x0133
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#define regSBRMI_WRITE_DATA1_BASE_IDX 0
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#define regSBRMI_WRITE_DATA2 0x0134
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#define regSBRMI_WRITE_DATA2_BASE_IDX 0
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#define regSBRMI_READ_DATA0 0x0136
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#define regSBRMI_READ_DATA0_BASE_IDX 0
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#define regSBRMI_READ_DATA1 0x0137
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#define regSBRMI_READ_DATA1_BASE_IDX 0
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#define regSBRMI_CORE_EN_NUMBER 0x0138
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#define regSBRMI_CORE_EN_NUMBER_BASE_IDX 0
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#define regSBRMI_CORE_EN_STATUS0 0x0139
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#define regSBRMI_CORE_EN_STATUS0_BASE_IDX 0
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#define regSBRMI_CORE_EN_STATUS1 0x013a
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#define regSBRMI_CORE_EN_STATUS1_BASE_IDX 0
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#define regSBRMI_APIC_STATUS0 0x013b
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#define regSBRMI_APIC_STATUS0_BASE_IDX 0
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#define regSBRMI_APIC_STATUS1 0x013c
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#define regSBRMI_APIC_STATUS1_BASE_IDX 0
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#define regSBRMI_MCE_STATUS0 0x013d
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#define regSBRMI_MCE_STATUS0_BASE_IDX 0
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#define regSBRMI_MCE_STATUS1 0x013e
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#define regSBRMI_MCE_STATUS1_BASE_IDX 0
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#define regSMBUS_CNTL0 0x013f
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#define regSMBUS_CNTL0_BASE_IDX 0
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#define regSMBUS_CNTL1 0x0140
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#define regSMBUS_CNTL1_BASE_IDX 0
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#define regSMBUS_BLKWR_CMD_CTRL0 0x0141
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#define regSMBUS_BLKWR_CMD_CTRL0_BASE_IDX 0
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#define regSMBUS_BLKWR_CMD_CTRL1 0x0142
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#define regSMBUS_BLKWR_CMD_CTRL1_BASE_IDX 0
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#define regSMBUS_BLKRD_CMD_CTRL0 0x0143
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#define regSMBUS_BLKRD_CMD_CTRL0_BASE_IDX 0
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#define regSMBUS_BLKRD_CMD_CTRL1 0x0144
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#define regSMBUS_BLKRD_CMD_CTRL1_BASE_IDX 0
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#define regSMBUS_TIMING_CNTL0 0x0145
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#define regSMBUS_TIMING_CNTL0_BASE_IDX 0
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#define regSMBUS_TIMING_CNTL1 0x0146
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#define regSMBUS_TIMING_CNTL1_BASE_IDX 0
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#define regSMBUS_TIMING_CNTL2 0x0147
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#define regSMBUS_TIMING_CNTL2_BASE_IDX 0
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#define regSMBUS_TRIGGER_CNTL 0x0148
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#define regSMBUS_TRIGGER_CNTL_BASE_IDX 0
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#define regSMBUS_UDID_CNTL0 0x0149
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#define regSMBUS_UDID_CNTL0_BASE_IDX 0
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#define regSMBUS_UDID_CNTL1 0x014a
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#define regSMBUS_UDID_CNTL1_BASE_IDX 0
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#define regSMBUS_UDID_CNTL2 0x014b
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#define regSMBUS_UDID_CNTL2_BASE_IDX 0
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#define regSMUSBI_SMBUS 0x014c
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#define regSMUSBI_SMBUS_BASE_IDX 0
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#define regSMUSBI_ALERT 0x014d
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#define regSMUSBI_ALERT_BASE_IDX 0
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#endif

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