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drm/amdgpu: add SMUIO 15.0.0 headers
Add headers for SMUIO 15.0.0. v2: squash in updates (Alex) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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‎drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_15_0_0_offset.h‎

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/*
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* Copyright (C) 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _smuio_15_0_0_OFFSET_HEADER
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#define _smuio_15_0_0_OFFSET_HEADER
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// addressBlock: smuio_smuio_misc_SmuSmuioDec
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// base address: 0x5a000
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#define regSMUIO_MCM_CONFIG 0x0023
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#define regSMUIO_MCM_CONFIG_BASE_IDX 0
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#define regIP_DISCOVERY_VERSION 0x0000
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#define regIP_DISCOVERY_VERSION_BASE_IDX 1
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#define regSCRATCH_REGISTER0 0x01c6
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#define regSCRATCH_REGISTER0_BASE_IDX 1
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#define regSCRATCH_REGISTER1 0x01c7
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#define regSCRATCH_REGISTER1_BASE_IDX 1
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#define regSCRATCH_REGISTER2 0x01c8
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#define regSCRATCH_REGISTER2_BASE_IDX 1
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#define regSCRATCH_REGISTER3 0x01c9
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#define regSCRATCH_REGISTER3_BASE_IDX 1
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#define regSCRATCH_REGISTER4 0x01ca
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#define regSCRATCH_REGISTER4_BASE_IDX 1
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#define regSCRATCH_REGISTER5 0x01cb
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#define regSCRATCH_REGISTER5_BASE_IDX 1
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#define regSCRATCH_REGISTER6 0x01cc
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#define regSCRATCH_REGISTER6_BASE_IDX 1
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#define regSCRATCH_REGISTER7 0x01cd
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#define regSCRATCH_REGISTER7_BASE_IDX 1
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#define regIO_SMUIO_PINSTRAP 0x01ce
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#define regIO_SMUIO_PINSTRAP_BASE_IDX 1
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// addressBlock: smuio_smuio_reset_SmuSmuioDec
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// base address: 0x5a300
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#define regSMUIO_GFX_MISC_CNTL 0x00c5
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#define regSMUIO_GFX_MISC_CNTL_BASE_IDX 0
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// addressBlock: smuio_smuio_tsc_SmuSmuioDec
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// base address: 0x5a8a0
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#define regPWROK_REFCLK_GAP_CYCLES 0x0028
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#define regPWROK_REFCLK_GAP_CYCLES_BASE_IDX 1
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#define regGOLDEN_TSC_INCREMENT_UPPER 0x002b
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#define regGOLDEN_TSC_INCREMENT_UPPER_BASE_IDX 1
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#define regGOLDEN_TSC_INCREMENT_LOWER 0x002c
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#define regGOLDEN_TSC_INCREMENT_LOWER_BASE_IDX 1
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#define regGOLDEN_TSC_COUNT_UPPER 0x0030
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#define regGOLDEN_TSC_COUNT_UPPER_BASE_IDX 1
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#define regGOLDEN_TSC_COUNT_LOWER 0x0031
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#define regGOLDEN_TSC_COUNT_LOWER_BASE_IDX 1
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#define regSOC_GOLDEN_TSC_SHADOW_UPPER 0x0032
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#define regSOC_GOLDEN_TSC_SHADOW_UPPER_BASE_IDX 1
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#define regSOC_GOLDEN_TSC_SHADOW_LOWER 0x0033
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#define regSOC_GOLDEN_TSC_SHADOW_LOWER_BASE_IDX 1
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#define regSOC_GAP_PWROK 0x0034
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#define regSOC_GAP_PWROK_BASE_IDX 1
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// addressBlock: smuio_smuio_swtimer_SmuSmuioDec
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// base address: 0x5aca8
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#define regPWR_VIRT_RESET_REQ 0x012a
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#define regPWR_VIRT_RESET_REQ_BASE_IDX 1
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#define regPWR_DISP_TIMER_CONTROL 0x012b
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#define regPWR_DISP_TIMER_CONTROL_BASE_IDX 1
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#define regPWR_DISP_TIMER_DEBUG 0x012c
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#define regPWR_DISP_TIMER_DEBUG_BASE_IDX 1
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#define regPWR_DISP_TIMER_ELAPSED_CONTROL 0x012d
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#define regPWR_DISP_TIMER_ELAPSED_CONTROL_BASE_IDX 1
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#define regPWR_DISP_TIMER2_CONTROL 0x012e
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#define regPWR_DISP_TIMER2_CONTROL_BASE_IDX 1
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#define regPWR_DISP_TIMER2_DEBUG 0x012f
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#define regPWR_DISP_TIMER2_DEBUG_BASE_IDX 1
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#define regPWR_DISP_TIMER2_ELAPSED_CONTROL 0x0130
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#define regPWR_DISP_TIMER2_ELAPSED_CONTROL_BASE_IDX 1
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#define regPWR_DISP_TIMER_GLOBAL_CONTROL 0x0131
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#define regPWR_DISP_TIMER_GLOBAL_CONTROL_BASE_IDX 1
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#define regPWR_IH_CONTROL 0x0132
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#define regPWR_IH_CONTROL_BASE_IDX 1
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#endif

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