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bjorn-helgaasjoergroedel
bjorn-helgaas
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joergroedel
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iommu/vt-d: Remove dmar_writel() and dmar_writeq()
dmar_writel() and dmar_writeq() do nothing other than expand to the generic writel() and writeq(), and the dmar_write*() wrappers are used inconsistently. Remove the dmar_write*() wrappers and use writel() and writeq() directly. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Samiullah Khawaja <skhawaja@google.com> Link: https://lore.kernel.org/r/20260217214438.3395039-3-bhelgaas@google.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
1 parent 9730091 commit 51234c4

6 files changed

Lines changed: 27 additions & 30 deletions

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‎drivers/iommu/intel/dmar.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1662,7 +1662,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
16621662
/* write zero to the tail reg */
16631663
writel(0, iommu->reg + DMAR_IQT_REG);
16641664

1665-
dmar_writeq(iommu->reg + DMAR_IQA_REG, val);
1665+
writeq(val, iommu->reg + DMAR_IQA_REG);
16661666

16671667
iommu->gcmd |= DMA_GCMD_QIE;
16681668
writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);

‎drivers/iommu/intel/iommu.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -697,7 +697,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
697697
addr |= DMA_RTADDR_SMT;
698698

699699
raw_spin_lock_irqsave(&iommu->register_lock, flag);
700-
dmar_writeq(iommu->reg + DMAR_RTADDR_REG, addr);
700+
writeq(addr, iommu->reg + DMAR_RTADDR_REG);
701701

702702
writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
703703

@@ -765,7 +765,7 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
765765
val |= DMA_CCMD_ICC;
766766

767767
raw_spin_lock_irqsave(&iommu->register_lock, flag);
768-
dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
768+
writeq(val, iommu->reg + DMAR_CCMD_REG);
769769

770770
/* Make sure hardware complete it */
771771
IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
@@ -806,8 +806,8 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
806806
raw_spin_lock_irqsave(&iommu->register_lock, flag);
807807
/* Note: Only uses first TLB reg currently */
808808
if (val_iva)
809-
dmar_writeq(iommu->reg + tlb_offset, val_iva);
810-
dmar_writeq(iommu->reg + tlb_offset + 8, val);
809+
writeq(val_iva, iommu->reg + tlb_offset);
810+
writeq(val, iommu->reg + tlb_offset + 8);
811811

812812
/* Make sure hardware complete it */
813813
IOMMU_WAIT_OP(iommu, tlb_offset + 8,
@@ -4201,8 +4201,8 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob)
42014201
* - It's not invoked in any critical path. The extra MMIO
42024202
* write doesn't bring any performance concerns.
42034203
*/
4204-
dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob);
4205-
dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT));
4204+
writeq(ob, iommu->reg + DMAR_ECEO_REG);
4205+
writeq(ecmd | (oa << DMA_ECMD_OA_SHIFT), iommu->reg + DMAR_ECMD_REG);
42064206

42074207
IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq,
42084208
!(res & DMA_ECMD_ECRSP_IP), res);

‎drivers/iommu/intel/iommu.h‎

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -148,9 +148,6 @@
148148

149149
#define OFFSET_STRIDE (9)
150150

151-
#define dmar_writeq(a,v) writeq(v,a)
152-
#define dmar_writel(a, v) writel(v, a)
153-
154151
#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
155152
#define DMAR_VER_MINOR(v) ((v) & 0x0f)
156153

‎drivers/iommu/intel/irq_remapping.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -465,8 +465,8 @@ static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
465465

466466
raw_spin_lock_irqsave(&iommu->register_lock, flags);
467467

468-
dmar_writeq(iommu->reg + DMAR_IRTA_REG,
469-
(addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
468+
writeq((addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE,
469+
iommu->reg + DMAR_IRTA_REG);
470470

471471
/* Set interrupt-remapping table pointer */
472472
writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);

‎drivers/iommu/intel/perfmon.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -99,20 +99,20 @@ IOMMU_PMU_ATTR(filter_page_table, "config2:32-36", IOMMU_PMU_FILTER_PAGE_TABLE);
9999
#define iommu_pmu_set_filter(_name, _config, _filter, _idx, _econfig) \
100100
{ \
101101
if ((iommu_pmu->filter & _filter) && iommu_pmu_en_##_name(_econfig)) { \
102-
dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \
103-
IOMMU_PMU_CFG_SIZE + \
104-
(ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \
105-
iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN);\
102+
writel(iommu_pmu_get_##_name(_config) | IOMMU_PMU_FILTER_EN, \
103+
iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \
104+
IOMMU_PMU_CFG_SIZE + \
105+
(ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \
106106
} \
107107
}
108108

109109
#define iommu_pmu_clear_filter(_filter, _idx) \
110110
{ \
111111
if (iommu_pmu->filter & _filter) { \
112-
dmar_writel(iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \
113-
IOMMU_PMU_CFG_SIZE + \
114-
(ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET, \
115-
0); \
112+
writel(0, \
113+
iommu_pmu->cfg_reg + _idx * IOMMU_PMU_CFG_OFFSET + \
114+
IOMMU_PMU_CFG_SIZE + \
115+
(ffs(_filter) - 1) * IOMMU_PMU_CFG_FILTERS_OFFSET); \
116116
} \
117117
}
118118

@@ -411,7 +411,7 @@ static int iommu_pmu_assign_event(struct iommu_pmu *iommu_pmu,
411411
hwc->idx = idx;
412412

413413
/* config events */
414-
dmar_writeq(iommu_config_base(iommu_pmu, idx), hwc->config);
414+
writeq(hwc->config, iommu_config_base(iommu_pmu, idx));
415415

416416
iommu_pmu_set_filter(requester_id, event->attr.config1,
417417
IOMMU_PMU_FILTER_REQUESTER_ID, idx,
@@ -510,7 +510,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu *iommu_pmu)
510510
iommu_pmu_event_update(event);
511511
}
512512

513-
dmar_writeq(iommu_pmu->overflow, status);
513+
writeq(status, iommu_pmu->overflow);
514514
}
515515
}
516516

@@ -524,7 +524,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void *dev_id)
524524
iommu_pmu_counter_overflow(iommu->pmu);
525525

526526
/* Clear the status bit */
527-
dmar_writel(iommu->reg + DMAR_PERFINTRSTS_REG, DMA_PERFINTRSTS_PIS);
527+
writel(DMA_PERFINTRSTS_PIS, iommu->reg + DMAR_PERFINTRSTS_REG);
528528

529529
return IRQ_HANDLED;
530530
}

‎drivers/iommu/intel/prq.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ static irqreturn_t prq_event_thread(int irq, void *d)
259259
head = (head + sizeof(*req)) & PRQ_RING_MASK;
260260
}
261261

262-
dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
262+
writeq(tail, iommu->reg + DMAR_PQH_REG);
263263

264264
/*
265265
* Clear the page request overflow bit and wake up all threads that
@@ -325,9 +325,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu)
325325
iommu->name);
326326
goto free_iopfq;
327327
}
328-
dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
329-
dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
330-
dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
328+
writeq(0ULL, iommu->reg + DMAR_PQH_REG);
329+
writeq(0ULL, iommu->reg + DMAR_PQT_REG);
330+
writeq(virt_to_phys(iommu->prq) | PRQ_ORDER, iommu->reg + DMAR_PQA_REG);
331331

332332
init_completion(&iommu->prq_complete);
333333

@@ -348,9 +348,9 @@ int intel_iommu_enable_prq(struct intel_iommu *iommu)
348348

349349
int intel_iommu_finish_prq(struct intel_iommu *iommu)
350350
{
351-
dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
352-
dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
353-
dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
351+
writeq(0ULL, iommu->reg + DMAR_PQH_REG);
352+
writeq(0ULL, iommu->reg + DMAR_PQT_REG);
353+
writeq(0ULL, iommu->reg + DMAR_PQA_REG);
354354

355355
if (iommu->pr_irq) {
356356
free_irq(iommu->pr_irq, iommu);

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