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bjorn-helgaasjoergroedel
bjorn-helgaas
authored and
joergroedel
committed
iommu/vt-d: Remove dmar_readl() and dmar_readq()
dmar_readl() and dmar_readq() do nothing other than expand to the generic readl() and readq(), and the dmar_read*() wrappers are used inconsistently. Remove the dmar_read*() wrappers and use readl() and readq() directly. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Samiullah Khawaja <skhawaja@google.com> Link: https://lore.kernel.org/r/20260217214438.3395039-2-bhelgaas@google.com Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>
1 parent c958721 commit 9730091

7 files changed

Lines changed: 46 additions & 48 deletions

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‎drivers/iommu/intel/debugfs.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -133,13 +133,13 @@ static int iommu_regset_show(struct seq_file *m, void *unused)
133133
*/
134134
raw_spin_lock_irqsave(&iommu->register_lock, flag);
135135
for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
136-
value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
136+
value = readl(iommu->reg + iommu_regs_32[i].offset);
137137
seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
138138
iommu_regs_32[i].regs, iommu_regs_32[i].offset,
139139
value);
140140
}
141141
for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
142-
value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
142+
value = readq(iommu->reg + iommu_regs_64[i].offset);
143143
seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
144144
iommu_regs_64[i].regs, iommu_regs_64[i].offset,
145145
value);
@@ -247,7 +247,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
247247
tbl_wlk.ctx_entry = context;
248248
m->private = &tbl_wlk;
249249

250-
if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
250+
if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
251251
pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
252252
pasid_dir_size = get_pasid_dir_size(context);
253253
pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
@@ -285,7 +285,7 @@ static int dmar_translation_struct_show(struct seq_file *m, void *unused)
285285

286286
rcu_read_lock();
287287
for_each_active_iommu(iommu, drhd) {
288-
sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
288+
sts = readl(iommu->reg + DMAR_GSTS_REG);
289289
if (!(sts & DMA_GSTS_TES)) {
290290
seq_printf(m, "DMA Remapping is not enabled on %s\n",
291291
iommu->name);
@@ -364,13 +364,13 @@ static int domain_translation_struct_show(struct seq_file *m,
364364
if (seg != iommu->segment)
365365
continue;
366366

367-
sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
367+
sts = readl(iommu->reg + DMAR_GSTS_REG);
368368
if (!(sts & DMA_GSTS_TES)) {
369369
seq_printf(m, "DMA Remapping is not enabled on %s\n",
370370
iommu->name);
371371
continue;
372372
}
373-
if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)
373+
if (readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT)
374374
scalable = true;
375375
else
376376
scalable = false;
@@ -538,8 +538,8 @@ static int invalidation_queue_show(struct seq_file *m, void *unused)
538538
raw_spin_lock_irqsave(&qi->q_lock, flags);
539539
seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
540540
(u64)virt_to_phys(qi->desc),
541-
dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
542-
dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
541+
readq(iommu->reg + DMAR_IQH_REG) >> shift,
542+
readq(iommu->reg + DMAR_IQT_REG) >> shift);
543543
invalidation_queue_entry_show(m, iommu);
544544
raw_spin_unlock_irqrestore(&qi->q_lock, flags);
545545
seq_putc(m, '\n');
@@ -620,7 +620,7 @@ static int ir_translation_struct_show(struct seq_file *m, void *unused)
620620
seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
621621
iommu->name);
622622

623-
sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
623+
sts = readl(iommu->reg + DMAR_GSTS_REG);
624624
if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
625625
irta = virt_to_phys(iommu->ir_table->base);
626626
seq_printf(m, " IR table address:%llx\n", irta);

‎drivers/iommu/intel/dmar.c‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -899,8 +899,8 @@ dmar_validate_one_drhd(struct acpi_dmar_header *entry, void *arg)
899899
return -EINVAL;
900900
}
901901

902-
cap = dmar_readq(addr + DMAR_CAP_REG);
903-
ecap = dmar_readq(addr + DMAR_ECAP_REG);
902+
cap = readq(addr + DMAR_CAP_REG);
903+
ecap = readq(addr + DMAR_ECAP_REG);
904904

905905
if (arg)
906906
iounmap(addr);
@@ -982,8 +982,8 @@ static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd)
982982
goto release;
983983
}
984984

985-
iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG);
986-
iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG);
985+
iommu->cap = readq(iommu->reg + DMAR_CAP_REG);
986+
iommu->ecap = readq(iommu->reg + DMAR_ECAP_REG);
987987

988988
if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) {
989989
err = -EINVAL;
@@ -1017,8 +1017,8 @@ static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd)
10171017
int i;
10181018

10191019
for (i = 0; i < DMA_MAX_NUM_ECMDCAP; i++) {
1020-
iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG +
1021-
i * DMA_ECMD_REG_STEP);
1020+
iommu->ecmdcap[i] = readq(iommu->reg + DMAR_ECCAP_REG +
1021+
i * DMA_ECMD_REG_STEP);
10221022
}
10231023
}
10241024

@@ -1239,8 +1239,8 @@ static const char *qi_type_string(u8 type)
12391239

12401240
static void qi_dump_fault(struct intel_iommu *iommu, u32 fault)
12411241
{
1242-
unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG);
1243-
u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
1242+
unsigned int head = readl(iommu->reg + DMAR_IQH_REG);
1243+
u64 iqe_err = readq(iommu->reg + DMAR_IQER_REG);
12441244
struct qi_desc *desc = iommu->qi->desc + head;
12451245

12461246
if (fault & DMA_FSTS_IQE)
@@ -1322,7 +1322,7 @@ static int qi_check_fault(struct intel_iommu *iommu, int index, int wait_index)
13221322
* SID field is valid only when the ITE field is Set in FSTS_REG
13231323
* see Intel VT-d spec r4.1, section 11.4.9.9
13241324
*/
1325-
iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG);
1325+
iqe_err = readq(iommu->reg + DMAR_IQER_REG);
13261326
ite_sid = DMAR_IQER_REG_ITESID(iqe_err);
13271327

13281328
writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG);
@@ -1981,8 +1981,8 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
19811981
source_id = dma_frcd_source_id(data);
19821982

19831983
pasid_present = dma_frcd_pasid_present(data);
1984-
guest_addr = dmar_readq(iommu->reg + reg +
1985-
fault_index * PRIMARY_FAULT_REG_LEN);
1984+
guest_addr = readq(iommu->reg + reg +
1985+
fault_index * PRIMARY_FAULT_REG_LEN);
19861986
guest_addr = dma_frcd_page_addr(guest_addr);
19871987
}
19881988

‎drivers/iommu/intel/iommu.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -769,7 +769,7 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
769769

770770
/* Make sure hardware complete it */
771771
IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
772-
dmar_readq, (!(val & DMA_CCMD_ICC)), val);
772+
readq, (!(val & DMA_CCMD_ICC)), val);
773773

774774
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
775775
}
@@ -811,7 +811,7 @@ void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
811811

812812
/* Make sure hardware complete it */
813813
IOMMU_WAIT_OP(iommu, tlb_offset + 8,
814-
dmar_readq, (!(val & DMA_TLB_IVT)), val);
814+
readq, (!(val & DMA_TLB_IVT)), val);
815815

816816
raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
817817

@@ -1533,7 +1533,7 @@ static int copy_translation_tables(struct intel_iommu *iommu)
15331533
int bus, ret;
15341534
bool new_ext, ext;
15351535

1536-
rtaddr_reg = dmar_readq(iommu->reg + DMAR_RTADDR_REG);
1536+
rtaddr_reg = readq(iommu->reg + DMAR_RTADDR_REG);
15371537
ext = !!(rtaddr_reg & DMA_RTADDR_SMT);
15381538
new_ext = !!sm_supported(iommu);
15391539

@@ -4188,7 +4188,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob)
41884188

41894189
raw_spin_lock_irqsave(&iommu->register_lock, flags);
41904190

4191-
res = dmar_readq(iommu->reg + DMAR_ECRSP_REG);
4191+
res = readq(iommu->reg + DMAR_ECRSP_REG);
41924192
if (res & DMA_ECMD_ECRSP_IP) {
41934193
ret = -EBUSY;
41944194
goto err;
@@ -4204,7 +4204,7 @@ int ecmd_submit_sync(struct intel_iommu *iommu, u8 ecmd, u64 oa, u64 ob)
42044204
dmar_writeq(iommu->reg + DMAR_ECEO_REG, ob);
42054205
dmar_writeq(iommu->reg + DMAR_ECMD_REG, ecmd | (oa << DMA_ECMD_OA_SHIFT));
42064206

4207-
IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, dmar_readq,
4207+
IOMMU_WAIT_OP(iommu, DMAR_ECRSP_REG, readq,
42084208
!(res & DMA_ECMD_ECRSP_IP), res);
42094209

42104210
if (res & DMA_ECMD_ECRSP_IP) {

‎drivers/iommu/intel/iommu.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,9 +148,7 @@
148148

149149
#define OFFSET_STRIDE (9)
150150

151-
#define dmar_readq(a) readq(a)
152151
#define dmar_writeq(a,v) writeq(v,a)
153-
#define dmar_readl(a) readl(a)
154152
#define dmar_writel(a, v) writel(v, a)
155153

156154
#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)

‎drivers/iommu/intel/irq_remapping.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -422,7 +422,7 @@ static int iommu_load_old_irte(struct intel_iommu *iommu)
422422
u64 irta;
423423

424424
/* Check whether the old ir-table has the same size as ours */
425-
irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
425+
irta = readq(iommu->reg + DMAR_IRTA_REG);
426426
if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
427427
!= INTR_REMAP_TABLE_REG_SIZE)
428428
return -EINVAL;

‎drivers/iommu/intel/perfmon.c‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -307,7 +307,7 @@ static void iommu_pmu_event_update(struct perf_event *event)
307307

308308
again:
309309
prev_count = local64_read(&hwc->prev_count);
310-
new_count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
310+
new_count = readq(iommu_event_base(iommu_pmu, hwc->idx));
311311
if (local64_xchg(&hwc->prev_count, new_count) != prev_count)
312312
goto again;
313313

@@ -340,7 +340,7 @@ static void iommu_pmu_start(struct perf_event *event, int flags)
340340
hwc->state = 0;
341341

342342
/* Always reprogram the period */
343-
count = dmar_readq(iommu_event_base(iommu_pmu, hwc->idx));
343+
count = readq(iommu_event_base(iommu_pmu, hwc->idx));
344344
local64_set((&hwc->prev_count), count);
345345

346346
/*
@@ -496,7 +496,7 @@ static void iommu_pmu_counter_overflow(struct iommu_pmu *iommu_pmu)
496496
* Two counters may be overflowed very close. Always check
497497
* whether there are more to handle.
498498
*/
499-
while ((status = dmar_readq(iommu_pmu->overflow))) {
499+
while ((status = readq(iommu_pmu->overflow))) {
500500
for_each_set_bit(i, (unsigned long *)&status, iommu_pmu->num_cntr) {
501501
/*
502502
* Find the assigned event of the counter.
@@ -518,7 +518,7 @@ static irqreturn_t iommu_pmu_irq_handler(int irq, void *dev_id)
518518
{
519519
struct intel_iommu *iommu = dev_id;
520520

521-
if (!dmar_readl(iommu->reg + DMAR_PERFINTRSTS_REG))
521+
if (!readl(iommu->reg + DMAR_PERFINTRSTS_REG))
522522
return IRQ_NONE;
523523

524524
iommu_pmu_counter_overflow(iommu->pmu);
@@ -555,7 +555,7 @@ static int __iommu_pmu_register(struct intel_iommu *iommu)
555555
static inline void __iomem *
556556
get_perf_reg_address(struct intel_iommu *iommu, u32 offset)
557557
{
558-
u32 off = dmar_readl(iommu->reg + offset);
558+
u32 off = readl(iommu->reg + offset);
559559

560560
return iommu->reg + off;
561561
}
@@ -574,7 +574,7 @@ int alloc_iommu_pmu(struct intel_iommu *iommu)
574574
if (!cap_ecmds(iommu->cap))
575575
return -ENODEV;
576576

577-
perfcap = dmar_readq(iommu->reg + DMAR_PERFCAP_REG);
577+
perfcap = readq(iommu->reg + DMAR_PERFCAP_REG);
578578
/* The performance monitoring is not supported. */
579579
if (!perfcap)
580580
return -ENODEV;
@@ -617,8 +617,8 @@ int alloc_iommu_pmu(struct intel_iommu *iommu)
617617
for (i = 0; i < iommu_pmu->num_eg; i++) {
618618
u64 pcap;
619619

620-
pcap = dmar_readq(iommu->reg + DMAR_PERFEVNTCAP_REG +
621-
i * IOMMU_PMU_CAP_REGS_STEP);
620+
pcap = readq(iommu->reg + DMAR_PERFEVNTCAP_REG +
621+
i * IOMMU_PMU_CAP_REGS_STEP);
622622
iommu_pmu->evcap[i] = pecap_es(pcap);
623623
}
624624

@@ -651,9 +651,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu)
651651
* Width.
652652
*/
653653
for (i = 0; i < iommu_pmu->num_cntr; i++) {
654-
cap = dmar_readl(iommu_pmu->cfg_reg +
655-
i * IOMMU_PMU_CFG_OFFSET +
656-
IOMMU_PMU_CFG_CNTRCAP_OFFSET);
654+
cap = readl(iommu_pmu->cfg_reg +
655+
i * IOMMU_PMU_CFG_OFFSET +
656+
IOMMU_PMU_CFG_CNTRCAP_OFFSET);
657657
if (!iommu_cntrcap_pcc(cap))
658658
continue;
659659

@@ -675,9 +675,9 @@ int alloc_iommu_pmu(struct intel_iommu *iommu)
675675

676676
/* Override with per-counter event capabilities */
677677
for (j = 0; j < iommu_cntrcap_egcnt(cap); j++) {
678-
cap = dmar_readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET +
679-
IOMMU_PMU_CFG_CNTREVCAP_OFFSET +
680-
(j * IOMMU_PMU_OFF_REGS_STEP));
678+
cap = readl(iommu_pmu->cfg_reg + i * IOMMU_PMU_CFG_OFFSET +
679+
IOMMU_PMU_CFG_CNTREVCAP_OFFSET +
680+
(j * IOMMU_PMU_OFF_REGS_STEP));
681681
iommu_pmu->cntr_evcap[i][iommu_event_group(cap)] = iommu_event_select(cap);
682682
/*
683683
* Some events may only be supported by a specific counter.

‎drivers/iommu/intel/prq.c‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,8 @@ void intel_iommu_drain_pasid_prq(struct device *dev, u32 pasid)
8181
*/
8282
prq_retry:
8383
reinit_completion(&iommu->prq_complete);
84-
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
85-
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
84+
tail = readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
85+
head = readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
8686
while (head != tail) {
8787
struct page_req_dsc *req;
8888

@@ -208,8 +208,8 @@ static irqreturn_t prq_event_thread(int irq, void *d)
208208
*/
209209
writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
210210

211-
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
212-
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
211+
tail = readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
212+
head = readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
213213
handled = (head != tail);
214214
while (head != tail) {
215215
req = &iommu->prq[head / sizeof(*req)];
@@ -268,8 +268,8 @@ static irqreturn_t prq_event_thread(int irq, void *d)
268268
if (readl(iommu->reg + DMAR_PRS_REG) & DMA_PRS_PRO) {
269269
pr_info_ratelimited("IOMMU: %s: PRQ overflow detected\n",
270270
iommu->name);
271-
head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
272-
tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
271+
head = readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
272+
tail = readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
273273
if (head == tail) {
274274
iopf_queue_discard_partial(iommu->iopf_queue);
275275
writel(DMA_PRS_PRO, iommu->reg + DMAR_PRS_REG);

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