Skip to content

Commit 34735f6

Browse files
John MadieuMani-Sadhasivam
authored andcommitted
PCI: rzg3s-host: Reorder reset assertion during suspend
Reorder the reset assertion sequence during suspend from power_resets -> cfg_resets to cfg_resets -> power_resets. This change ensures the suspend sequence follows the reverse order of the probe/init sequence, where power_resets are deasserted first followed by cfg_resets. Additionally, this ordering is required for RZ/G3E support where cfg resets are controlled through PCIe AXI registers (offset 0x310h). According to the RZ/G3E hardware manual (Rev.1.15, section 6.6.6.1.1 "Changing the Initial Values of the Registers"), AXI register access requires ARESETn to be de-asserted and the clock to be supplied. Since ARESETn is part of power_resets, cfg_resets must be asserted before power_resets, otherwise the AXI registers become inaccessible. Fixes: 7ef502f ("PCI: Add Renesas RZ/G3S host controller driver") Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> # RZ/V2N EVK Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://patch.msgid.link/20260306143423.19562-3-john.madieu.xa@bp.renesas.com
1 parent d284389 commit 34735f6

1 file changed

Lines changed: 9 additions & 9 deletions

File tree

drivers/pci/controller/pcie-rzg3s-host.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1624,31 +1624,31 @@ static int rzg3s_pcie_suspend_noirq(struct device *dev)
16241624

16251625
clk_disable_unprepare(port->refclk);
16261626

1627-
ret = reset_control_bulk_assert(data->num_power_resets,
1628-
host->power_resets);
1627+
ret = reset_control_bulk_assert(data->num_cfg_resets,
1628+
host->cfg_resets);
16291629
if (ret)
16301630
goto refclk_restore;
16311631

1632-
ret = reset_control_bulk_assert(data->num_cfg_resets,
1633-
host->cfg_resets);
1632+
ret = reset_control_bulk_assert(data->num_power_resets,
1633+
host->power_resets);
16341634
if (ret)
1635-
goto power_resets_restore;
1635+
goto cfg_resets_restore;
16361636

16371637
ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B,
16381638
RZG3S_SYS_PCIE_RST_RSM_B_MASK,
16391639
FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0));
16401640
if (ret)
1641-
goto cfg_resets_restore;
1641+
goto power_resets_restore;
16421642

16431643
return 0;
16441644

16451645
/* Restore the previous state if any error happens */
1646-
cfg_resets_restore:
1647-
reset_control_bulk_deassert(data->num_cfg_resets,
1648-
host->cfg_resets);
16491646
power_resets_restore:
16501647
reset_control_bulk_deassert(data->num_power_resets,
16511648
host->power_resets);
1649+
cfg_resets_restore:
1650+
reset_control_bulk_deassert(data->num_cfg_resets,
1651+
host->cfg_resets);
16521652
refclk_restore:
16531653
clk_prepare_enable(port->refclk);
16541654
pm_runtime_resume_and_get(dev);

0 commit comments

Comments
 (0)