config: arrowlake-h enabling

[Karabiner07]

Summary

Add Arrow Lake-H (family 6, model 0xC5/197) platform support:

• Add model 0xC5 to the supported platform table in lpmd_cpu.c
• Add intel_lpmd_config_F6_M197.xml with WLT-driven power management tuned for H-series hybrid topology
• Register the new config in data/Makefile.am

Design

Arrow Lake-H uses a P+E+L hybrid topology. The config keeps P-cores permanently parked in Balanced/AUTO mode — all differentiation is done via per-state EPP/EPB within the E+L core set. Users who need P-cores select Performance mode or disable LPMD.

Power profile mapping:

Profile	Def	Mode	Active cores
Performance	-1	LPMD OFF	All (P+E+L)
Balanced	0	AUTO	E+L only
Power Saver	1	Force ON	L only

Unlike upstream templates (all Defs=-1 / idle by default), this config is active out-of-the-box with BalancedDef=0 and PowersaverDef=1.

WLT states (Balanced/AUTO mode):

State	WLT	EPP	EPB	Rationale
UTIL_IDLE	0+1 (WLTTypeMask=3)	192 "balance_power"	8	Idle / light usage — power-biased
UTIL_IDLE_SUSTAIN	2	64	4	Sustained compute — E-cores boost
UTIL_IDLE_BURSTY	3	128 "balance_performance"	6	Burst absorption — moderate

All states use ActiveLcores=ALL + ActiveEcores=ALL (topology-portable, resolved at runtime via CPUID) with IRQMigrate=1 and Mode=1 (cgroup v2 isolate).

Key decisions

• WLT 0/1 merge (WLTTypeMask=3): Hardware oscillates between WLT_IDLE and WLT_BATTERY_LIFE ~2x/sec. Separate states with different EPP/EPB values would cause ~64 sysfs writes/sec of I/O churn. Merging them into one state eliminates this entirely. Pattern adopted from F6_M181 (Arrow Lake-U).

• No wildcard WLT state: Some configs (e.g. F6_M189) use a wildcard state with no WLTType to catch invalid values. Here, invalid/out-of-range WLT values (e.g. WLT_INVALID=4) match no state — the daemon holds its current state unchanged (STATE_NONE), producing zero writes on garbage data.

• Util thresholds disabled: All AUTO states share the same CPU mask (E+L), so load-based exit adds no value. The power-performance spectrum is handled entirely by EPP/EPB per WLT state.

• ITMT: IgnoreITMT=0 for upstream consistency. Effectively a no-op — the kernel 6.14+ debugfs toggle is not created on Arrow Lake-H, and ITMT (prefer P-cores) conflicts with LPM (park P-cores).

• SoC Power Slider: Omitted. Panther Lake hardware debut; Arrow Lake loads the module but does not expose the slider mailbox.

Files changed

• src/lpmd_cpu.c — Add model 0xC5 to id_table[], fix 0xB5 comment ("ArrowLake" → "Arrowlake U")
• data/intel_lpmd_config_F6_M197.xml — New platform config (documented inline)
• data/Makefile.am — Register config for installation

Test plan

• Verified on Intel Core Ultra 7 255H (6P+8E+2L, 28W, kernel 6.17.0-35-generic)
• Tested all profile transitions: Performance → Balanced → Power Saver → Balanced → Performance
• Confirmed P-cores parked in Balanced (cgroup cpuset.cpus = E+L set)
• Confirmed WLTTypeMask=3 suppresses WLT 0↔1 oscillation (zero state transitions during rapid WLT toggling)
• Confirmed cgroup skip optimization ("Skip cgroup: cpumask unchanged") when transitioning between states with same CPU mask
• Confirmed three-tier EPP differentiation: 192/64/128 applied per WLT state
• Confirmed clean shutdown: EPP restored to profile baseline, cgroup partitions reset to "member"
• logs to verify runtime power profile switching: new-logs.txt