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insper-riscv
Insper-RISC-V
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Complete merge of agentic work
- #49
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Complete merge of agentic work
#49
Peng1104
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insper-riscv/Insper-RISC-V:main
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final
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Commits
Commits on Oct 5, 2026
make board-build / board: build in the toolchain image, run on the board
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Commits on Oct 12, 2026
Benchmark the SDRAM platform and pin the submodules it was measured on
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Add the board benchmark of the SDRAM self test
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Add the full-platform board run to the SDRAM board benchmark
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Fix the core-domain slack and drop the compile time in the board benchmark
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Board benchmark: the run on the published toolchain image
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Commits on Oct 15, 2026
add UART implementation plan
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update peripherals w UART implementation
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atualizando integracao da UART no projeto
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Commits on Oct 26, 2026
feat: validate UART with separate TX and RX registers
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test: integrate UART error and burst validation
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Docs: autores 2026.1, norma C23 e guias bilíngues
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ci: update TopLevel UART workflow
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Commits on Oct 27, 2026
Register the Infra submodule and use SSH URLs for the submodules
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Merge origin/UART
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Merge origin/agent/docs-authors-c23
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Merge make board-build: build in the toolchain image
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Point every submodule at its final branch and add the Certification submodule
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Add the Common-Components submodule and point every submodule at its final branch
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Run the workflows on the ci-* images and take the final submodules
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Update Common-Components (authors and citation)
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Update Core (README)
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Update Tests (misaligned trap test)
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Take the Common-Components sources in src/ and the new tests
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Point the submodules at the Common-Components tests, authors and CONTRIBUTING updates
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Point Common-Components at the corrected contribution guide
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Point Common-Components at its main
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Point the submodules at the Tools whose tests pass pyright strict
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Follow the Infra rename: ci-asm is now ci-elf and ci-elf is now ci-act4
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Point the submodules at the Infra rename
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