All pull requests

Pull requests

• Final: all open PRs merged, Common-Components submodule, Zicclsm

  #14·Peng1104 opened Oct 28, 2026Contributor·

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• ACT4 stack in one PR: baseline, divider fix, Zicsr, traps, SDRAM fetch, formal CSR properties and registered M stall (#5 to #12)

  #13·peng1104-agent[bot] opened Oct 26, 2026Bot·

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• M stall driven by a flip-flop: the completion pulse leaves the pipeline stall logic

  #12·peng1104-agent[bot] opened Oct 24, 2026Bot·3 tasks done·

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• Formal CSR properties for the async-reset register file

  #11·peng1104-agent[bot] opened Oct 24, 2026Bot·1 task done·

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• Instruction fetch from the SDRAM with a ready handshake, and FENCE.I

  #10·peng1104-agent[bot] opened Oct 24, 2026Bot·4 tasks done·

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• Machine-mode traps: trap unit, ecall, ebreak, mret, misaligned accesses and formal proofs

  #9·peng1104-agent[bot] opened Oct 23, 2026Bot·5 tasks done·

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• Zicsr: CSR decoder, machine-mode CSR bank and the rv32im_zicsr profile

  #8·peng1104-agent[bot] opened Oct 23, 2026Bot·4 tasks done·

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• Divider: 34-bit partial remainder for DIVU and REMU

  #7·peng1104-agent[bot] opened Oct 23, 2026Bot·

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• Baseline for the ACT4 plan

  #6·peng1104-agent[bot] opened Oct 23, 2026Bot·

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• Stall the pipeline on a variable-latency data memory (SDRAM)

  #5·Peng1104 opened Oct 5, 2026Contributor·

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