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1. Design-of-AMBA-APB-Slave-UART-Wrapper Design-of-AMBA-APB-Slave-UART-Wrapper Public

   Verilog

2. FIR-Filter-Design-Using-Distributed-Arithmetic-for-Better-PPA FIR-Filter-Design-Using-Distributed-Arithmetic-for-Better-PPA Public

   Verilog

3. RISCV RISCV Public

   Verilog

4. Syncronous-FIFO Syncronous-FIFO Public

   HTML

5. eda-3d-routing-challenge eda-3d-routing-challenge Public

   Forked from partcleda/eda-3d-routing-challenge

   M3D routing challenge: a reproducible EDA routing benchmark for a simplified monolithic-3D stack (generator, checker, scorer, baseline, visualization).

   Python

6. FFT_8pt FFT_8pt Public

   Design Of 8 Point Pipelined FFT in Verilog

   Verilog