FPGA Signal Processing

A collection of VHDL implementations and supporting MATLAB scripts for exploring digital signal-processing pipelines on FPGA hardware. These modules progresses from foundational logic and arithmetic blocks to a sampled-data processing chain incorporating Direct Digital Synthesis (DDS) generation to simulate analog waves by loading waveform data from BRAM memory, windowing, FFT, CORDIC, filtering, and Hilbert-transform processing for Basys-3-board.

These modules were developed throughout a short course on FPGA signal processing course hosted by SNC. All modules were tested in simulation using Vivado and MATLAB, and the top-level demonstrations were tested on Basys-3 FPGA hardaware.

Main DSP blocks

All design sources are in src directory

1. Fundamental logic and control

Module	Description
xor2.vhd	Two-input XOR gate.
and3.vhd	Three-input AND gate.
reg_xor2.vhd	Registered two-input XOR gate.
reg_and3.vhd	Registered three-input AND gate.
counter.vhd	Parameterised synchronous counter with enable, limit, and done output.
decoder4.vhd	Four-bit decoder.
encoder_16_4.vhd	16-to-4 encoder.
state_machine.vhd	State-machine example.
lfsr32.vhd	32-bit linear-feedback shift register.
rom_rand_module.vhd	ROM-based random-data source.

2. Arithmetic and sample-processing blocks

Module	Description
mult.vhd	Registered real multiplier.
accum.vhd	Parameterised signed accumulator.
maf4.vhd	Four-sample moving-average filter.
noise_gen.vhd	Noise generator that combines four seeded 32-bit LFSRs.
vadc.vhd	Virtual ADC that plays generated waveform data from vadc_pkg.
dds.vhd	Direct digital synthesiser with a phase accumulator and sine/cosine lookup table.
win.vhd	1024-sample windowing block using coefficients from win_pkg.
cmult.vhd	Pipelined complex multiplier.

3. DSP pipelines and IP-based processing

Module	Description
cfir.vhd	Complex FIR filter composed of real and imaginary Xilinx FIR IP cores.
hilbert.vhd	I/Q signal path combining DDS mixing, complex multiplication, and filtering.
top_fft.vhd	Virtual-ADC source connected to the 1024-point Xilinx FFT IP core.
top_cordic.vhd	FFT output connected to Xilinx CORDIC IP for magnitude/phase processing.

Xilinx IP blocks

The following Vivado IP configurations are stored in src.srcs/sources_1/ip/ and are used by the DSP demonstrations:

IP block	Purpose	Used by
fft_1024	1024-point streaming FFT.	top_fft.vhd, top_cordic.vhd, and top_win.vhd
xfft_0	Additional Xilinx FFT configuration retained in the project.	Available for FFT experiments
cordic_16	CORDIC processing for FFT magnitude and phase.	top_cordic.vhd, top_win.vhd
fir_lpf	Low-pass FIR filter.	top_fir.vhd
fir_real	FIR filter for the real-path terms of the complex FIR.	cfir.vhd
fir_imag	FIR filter for the imaginary-path terms of the complex FIR.	cfir.vhd

4. Top-level demonstrations

Module	Description
top.vhdl	Basic LED/switch top-level example.
top2.vhd	Combinational XOR/AND hierarchy demonstration.
top3.vhd	Registered XOR/AND hierarchy demonstration.
top_counter.vhd	Counter demonstration.
top_decoder4.vhd	Decoder demonstration.
encoder16_4_top.vhd	16-to-4 encoder demonstration.
top_encoder16_4.vhd	Alternative 16-to-4 encoder top-level.
top_mult.vhd	Multiplier demonstration with counter and ROM stimulus.
top_accum.vhd	Accumulator demonstration with counter and ROM stimulus.
top_cmult.vhd	Complex-multiplier demonstration with counter and ROM stimulus.
top_noise_gen.vhd	Noise-generator demonstration.
top_vadc.vhd	Virtual-ADC demonstration.
top_win.vhd	Windowing, FFT, and CORDIC demonstration.
top_hilbert.vhd	Hilbert I/Q processing demonstration.
top_fir.vhd	Hilbert output connected to low-pass FIR IP.
top_cfir.vhd	Complex-FIR demonstration.

Schematics

Block diagrams of the main modules, generated from the VHDL source with GHDL, Yosys, and netlistsvg. Clock and reset are hidden, and signals marked mark_debug are drawn as outputs labelled (ILA).

To regenerate them (requires ghdl, netlistsvg, and the Yosys from OSS CAD Suite):

make diagram

Arithmetic and sample-processing blocks

Registered real multiplier (mult)

Signed accumulator (accum)

Four-sample moving-average filter (maf4)

Noise generator (noise_gen)

Virtual ADC (vadc)

Direct digital synthesiser (dds)

Windowing block (win)

Complex multiplier (cmult)

DSP pipelines

Complex FIR filter (cfir)

Hilbert I/Q signal path (hilbert)

Top-level pipelines

Hilbert output into low-pass FIR (top_fir)

Virtual ADC into FFT (top_fft)

FFT into CORDIC (top_cordic)

Windowing, FFT and CORDIC (top_win)

Test Benches

All the modules were tested with VHDL test benches located in the Vivado project under src.srcs/sim_1. MATLAB was used to generate test vectors and plot results for the FIR, Hilbert, and CORDIC processing blocks. The MATLAB scripts are located in the Matlab/ directory.

For example the cordic_tb.m generates test vectors for the top_cordic.vhd demonstration. The test bench waveform is shown below.