chore(deps): bump arc-gic to 0.10 and arm-sysregs to 0.5

Cargo.toml

@@ -22,7 +22,7 @@ aarch64-paging = "0.12"
 aarch64-rt = { version = "0.4.3", features = ["el2", "exceptions", "initial-pagetable", "psci"], default-features = false }
 arm-pl011-uart = "0.5"
 arm-psci = "0.2"
-arm-sysregs = { version = "0.3", features = ["el1", "el2"] }
+arm-sysregs = { version = "0.5", features = ["el1", "el2"] }
 arrayvec = { version = "0.7", default-features = false }
 buddy_system_allocator = { version = "0.13", default-features = false, features = ["alloc", "use_spin"] }
 dtoolkit = { version = "0.4", features = ["write"] }

src/arch.rs

@@ -8,7 +8,7 @@
 
 //! Architecture-specific code.
 
-use arm_sysregs::{SctlrEl2, read_sctlr_el2};
+use arm_sysregs::el2::{accessors::read_sctlr_el2, registers::SctlrEl2};
 use core::arch::{asm, naked_asm};
 
 /// Data Synchronization Barrier.

src/hypervisor.rs

@@ -18,14 +18,24 @@ use crate::{
     },
 };
 use aarch64_rt::Stack;
-use arm_sysregs::{
-    CnthctlEl2, CntvoffEl2, ElrEl1, ElrEl2, EsrEl1, FarEl1, HcrEl2, IccSreEl2, MairEl1, MpidrEl1,
-    SctlrEl1, SpEl1, SpsrEl1, SpsrEl2, TcrEl1, Ttbr0El1, VbarEl1, VtcrEl2, read_cnthctl_el2,
-    read_esr_el2, read_far_el2, read_hpfar_el2, read_icc_sre_el2, read_mpidr_el1, read_spsr_el2,
-    read_vbar_el1, write_cnthctl_el2, write_cntvoff_el2, write_elr_el1, write_elr_el2,
-    write_esr_el1, write_far_el1, write_hcr_el2, write_icc_sre_el2, write_mair_el1,
-    write_sctlr_el1, write_sp_el1, write_spsr_el1, write_spsr_el2, write_tcr_el1, write_ttbr0_el1,
-    write_vbar_el1, write_vtcr_el2,
+use arm_sysregs::el1::{
+    accessors::{
+        read_mpidr_el1, read_vbar_el1, write_elr_el1, write_esr_el1, write_far_el1, write_mair_el1,
+        write_sctlr_el1, write_sp_el1, write_spsr_el1, write_tcr_el1, write_ttbr0_el1,
+        write_vbar_el1,
+    },
+    registers::{
+        ElrEl1, EsrEl1, FarEl1, MairEl1, MpidrEl1, SctlrEl1, SpEl1, SpsrEl1, TcrEl1, Ttbr0El1,
+        VbarEl1,
+    },
+};
+use arm_sysregs::el2::{
+    accessors::{
+        read_cnthctl_el2, read_esr_el2, read_far_el2, read_hpfar_el2, read_icc_sre_el2,
+        read_spsr_el2, write_cnthctl_el2, write_cntvoff_el2, write_elr_el2, write_hcr_el2,
+        write_icc_sre_el2, write_spsr_el2, write_vtcr_el2,
+    },
+    registers::{CnthctlEl2, CntvoffEl2, ElrEl2, HcrEl2, IccSreEl2, SpsrEl2, VtcrEl2},
 };
 use core::arch::naked_asm;
 use log::debug;

src/main.rs

@@ -26,7 +26,7 @@ include!(concat!(env!("OUT_DIR"), "/payload.rs"));
 
 use aarch64_paging::paging::PAGE_SIZE;
 use aarch64_rt::{entry, exception_handlers};
-use arm_sysregs::read_currentel;
+use arm_sysregs::el0::accessors::read_currentel;
 use buddy_system_allocator::{Heap, LockedHeap};
 use core::alloc::Layout;
 use core::arch::naked_asm;

tests/integration_test/Cargo.toml

@@ -7,6 +7,6 @@ publish = false
 [dependencies]
 aarch64-rt = { version = "0.4", features = ["el1", "exceptions"], default-features = false }
 arm-pl011-uart = "0.5"
-arm-sysregs = { version = "0.3", features = ["el1"] }
+arm-sysregs = { version = "0.5", features = ["el1"] }
 smccc = "0.2"
 spin = { version = "0.12", features = ["lazy", "once", "spin_mutex"], default-features = false }

tests/integration_test/src/main.rs

@@ -11,7 +11,7 @@
 
 use aarch64_rt::{ExceptionHandlers, RegisterStateRef, entry, exception_handlers};
 use arm_pl011_uart::{Uart, UniqueMmioPointer};
-use arm_sysregs::read_esr_el1;
+use arm_sysregs::el1::accessors::read_esr_el1;
 use core::arch::{asm, naked_asm};
 use core::fmt::Write;
 use core::panic::PanicInfo;

tests/psci_test/Cargo.toml

@@ -6,10 +6,10 @@ publish = false
 
 [dependencies]
 aarch64-rt = { version = "0.4", features = ["el1", "exceptions", "psci"], default-features = false }
-arm-gic = "0.8"
+arm-gic = "0.10"
 arm-pl011-uart = "0.5"
 arm-psci = "0.2"
-arm-sysregs = { version = "0.3", features = ["el1"] }
+arm-sysregs = { version = "0.5", features = ["el1"] }
 percore = { version = "0.3", default-features = false }
 smccc = "0.2"
 spin = "0.12"