stm32: program the ST SWO/SWTF trace blocks for H7 SWO (issue-41)

[emrainey]

Summary

Closes #41. Programs the ST Serial Wire Output path on the STM32H7 so the Cortex-M7 ITM trace stream reaches the SWO pin (PB3 / TRACESWO). On the H7 the ARM CoreSight TPIU does not drive the SWO pin — the ST SWO (0x5C003000) and SWTF funnel (0x5C004000) blocks do.

What changed

• New register headers stm32/h7xx/Swo.hpp + SwoTraceFunnel.hpp (hand-written, peripheralyzer style, offsets static_asserted), UNITTEST RAM globals, and linker PROVIDEs for both debug blocks.
• enable_serial_wire_output(trace_clock, baud) (H7 debug.cpp): enables DBGMCU TRACECLKEN/D1DBGCKEN/D3DBGCKEN, unlocks SWO/SWTF (0xC5ACCE55), selects Async-NRZ, programs SWO_CODR from TRACECK (= PLL1R), enables the SWTF. F4 gets a documented no-op (its standard TPIU drives SWO).
• ClockTree.trace: computed in clocks.cpp (PLL1R on H7, sysclk on F4) and the vendor call invoked from clocks() — required because module archives are scanned once before jarnax, so vendor symbols referenced only from configure.cpp never link (same issue as early_power, FIXME at clocks.cpp:38).
• BoardContext: PB3 configured as TRACESWO (AF0, very-high speed).
• Demo: periodic SWO-OK marker on the SWO System port for verification.
• Tests: 10 new gtest cases over the UNITTEST globals.

Verification

• M4/M7 cross (+ -ci) and host llvm/clang presets build clean; on-host-native-gcc excluded (documented Darwin-only failure).
• Hardware (Nucleo-H753ZI), single-session breakpoint dump at cortex::system::main():
  • DBGMCU_CR = 0x00700007 (trace/debug clocks on)
  • SWO_CODR = 0x2b → 100 MHz / 2.24 MBaud
  • SWO_SPPR = 2 → AsyncNRZ (UART)
  • SWTF_CTRL = 0x301 → ENSO enabled

Note: a J-Link reconnect rewrites DBGMCU_CR to 0x07, unclocking the D3 debug domain — register reads are only valid within a single debug session (see GOTCHAS.md).

Follow-ups

• SWO byte capture on the J-Link probe needs tooling (issue jalo.py: add SWO (Serial Wire Output) trace viewer #54).
• Cold-POR boot hard-fault observed during bring-up tracked in issue Cold power-on reset hard-faults before configure() (CFSR IMPREISERR, HFSR 0xC0000000) #55.