[NAVEENKUMARKR777]

Implemented complete PWM (Pulse Width Modulation) peripheral driver with platform-specific implementations for STM32F4 hardware and host systems (Windows/Linux/macOS).

Key Features

• STM32F4 Hardware Implementation: Register-level PWM using TIM2-TIM5 timers with 16 channels, dynamic frequency/duty control, and proper timer configuration
• Cross-Platform Host Backend: Windows/Linux/macOS compatible simulation for testing
• Extended HAL Integration: Added PWM to extended HAL backend registration system
• Comprehensive Testing: 25 unit tests with 100% pass rate covering API validation, error handling, multi-channel support, and edge cases

Impact

• Moves PWM from "Planned" to "Experimental" status in STATUS.md
• Enables motor control, LED dimming, servo control, and power regulation capabilities
• Provides production-ready foundation for embedded applications requiring real-time control

Testing

• All 25 unit tests pass (25/25)
• Verified on Windows host build
• Cross-platform compatibility ensured

Files Changed

• hal/src/hal_pwm.c (NEW - 383 lines)
• tests/test_pwm.c (NEW - 421 lines)
• CMakeLists.txt (build integration)
• hal/include/eos/hal_extended.h (extended HAL backend)
• hal/src/hal_extended_stubs.c (removed PWM stubs)
• tests/CMakeLists.txt (test integration)
• products/vbox_test.h (enabled PWM for testing)
• STATUS.md (updated implementation status)

[srpatcha]

Review — eos#136 "feat(hal): implement PWM peripheral with dual-platform support"

head: 96d9f6d author: NAVEENKUMARKR777 ci: pending (no checks reported on the branch)

Verdict: Does not conform. The host half is sound and the 25 tests genuinely pass, but the STM32F4 half writes past the end of its state array for every channel above 3 (ASan-confirmed), divides by zero on frequency_hz == 0, and is compiled by no build target in this repository — so none of the 25 tests touch a line of it. On that basis the PR moves the STATUS.md row from Planned to Experimental and additionally asserts that ADC "passes basic tests", when no ADC test exists in the suite. §28's evidence model is not satisfied for the claim being made.

Findings

#	Severity	File:line	Finding	Recommended fix
1	Critical	hal/src/hal_pwm.c:85	pwm_state[4] is declared with 4 entries and indexed by the raw channel number, which hal_pwm.c:92 bounds only at >= 16. Channels 4–15 write and read past the end of the array: writes at :155-158, reads at :196, :221, :269, :284, and full 16-iteration scans at :179 and :293. The host half gets this right — host_pwm_state[16] at :332 — so it is the STM32F4 array alone that is wrong. On a Cortex-M target there is no MMU and no allocator guard, so this silently corrupts whatever static object the linker placed after pwm_state, and eos_pwm_init() still returns 0. The garbage initialized byte read at :196/:269 also lets set_duty(7, …) and start(7) proceed into timer-register writes whenever the adjacent byte happens to be non-zero. Verified — see the ASan trace below.	} pwm_state[16] = {0};. One number. It must land together with a test that covers channels 4–15 on this branch, or nothing in the repo will notice it again.
2	High	hal/src/hal_pwm.c:115 and :119	timer_clock / cfg->frequency_hz with cfg->frequency_hz never validated. eos_pwm_set_freq() does check frequency_hz == 0 (:219); eos_pwm_init() does not, so the zero comes straight from caller config into an integer divide. Verified: UBSan reports division by zero at :115. On Cortex-M4 UDIV by zero yields 0 or raises a HardFault depending on CCR.DIV_0_TRP, so the behaviour is target-configuration dependent — the worst kind.	Add `
3	High	STATUS.md:38	The row asserts "ADC has STM32F4 implementation and passes basic tests." This PR does not touch ADC, and there is no ADC test: ctest -N on this branch lists 39 tests and none of them is an ADC suite (ls tests/ | grep -i adc is empty). Under §28 that is a claim with no evidence, inserted about a subsystem outside the diff — and STATUS.md's own preamble says an unmeasured claim "should be driven to zero". The same row also still reads "144 (void)param; casts", which this PR reduced by six functions.	Delete the ADC sentence. It is unrelated to this PR and unsupported. Update the cast count to what the branch actually contains.
4	High	hal/src/hal_pwm.c:19-312	The entire STM32F4 implementation — 220 of the file's 389 lines — is compiled by nothing in this repository. Verified two ways: (a) EOS_MCU_STM32F4 is set as a CMake cache variable in toolchains/arm-cortex-m4.cmake:29 and is never converted into a compile definition — grep -rn EOS_MCU_STM32F4 cmake/ CMakeLists.txt returns nothing, so the CMake cross build does not define it to the preprocessor either; (b) the ARM CI job at .github/workflows/build.yml:82-107 compiles an explicit source list that does not include hal/src/hal_pwm.c, and its flags do not set EOS_ENABLE_PWM, so both conditions of the #if at :19 would still be false. Consequently all 25 passing tests execute the host branch at :314-389, which stores four values in a struct. The advertised "25 unit tests with 100% pass rate" is true and covers zero of the hardware code.	Do not fix the build wiring inside this PR — it is a separate change with its own blast radius (it would start compiling the pre-existing STM32F4 branches of hal_extended.c and hal_rtos.c for the first time too). Instead: say so in the PR body, and do not upgrade the STATUS.md row on the strength of the host tests. Once the wiring exists, the ARM job must compile this file and fail on -Wall -Wextra.
5	Medium	hal/include/eos/hal_extended.h:974-981	The six pwm_* function pointers added to the public eos_hal_ext_backend_t are never assigned and never called. Verified: s_ext_backend is written only by eos_hal_register_ext_backend() (hal/src/hal_extended_stubs.c:22-26) and read only by eos_hal_get_ext_backend() (:29-32); no ->pwm_* call site exists anywhere in the tree. So the backend table is a write-only registry, hal_pwm.c defines eos_pwm_* as direct globals that bypass it, and this PR widens a public header for no consumer — .ai/architect.md "Do not widen a public header to make one caller compile", here for zero callers. Second-order: the new members sit behind #if EOS_ENABLE_PWM, so sizeof(eos_hal_ext_backend_t) now differs between a library and an application that disagree about that macro. That hazard pre-exists for the other conditional members, but this PR adds to it, and §23.2 makes "EoS ABI" a versioned contract.	Either drop the six pointers from this PR — they add nothing and the header change is then zero — or wire the dispatch: have eos_pwm_* consult eos_hal_get_ext_backend() and fall through to the built-in implementation, the way the header's own example at :874-883 implies. The first option is correct for this PR; the second is a separate design change.
6	Medium	hal/src/hal_pwm.c:178-188	eos_pwm_deinit() decides whether to stop the timer by scanning all 16 channels without checking which timer they belong to, unlike eos_pwm_stop() at :292-303, which correctly filters on channel_to_timer[i] == timer_idx. So deinitialising the last active channel of TIM2 leaves TIM2 running whenever any channel on TIM3/4/5 is running, and stops TIM2 out from under nothing when they are all idle. The two functions implement the same decision two different ways, and one of them is wrong.	Copy the channel_to_timer[i] == timer_idx condition from :294 into :180. Better: factor the scan into one static bool timer_has_active_channel(uint8_t timer_idx, uint8_t except_channel) used by both, so they cannot drift again.
7	Medium	hal/src/hal_pwm.c:92	cfg->duty_pct_x10 is not validated in eos_pwm_init(), while eos_pwm_set_duty() rejects > 1000 at :194. Verified: eos_pwm_init() with duty_pct_x10 = 65535 returns 0 and programs CCR = period * 65535 / 1000, far above ARR — the output sits at 100% with no error. The same parameter is validated on one path and not the other.	Add `
8	Medium	hal/src/hal_pwm.c:115-120	Unsigned underflow for frequency_hz > 84000000: 84000000 / frequency_hz is 0, so - 1 wraps to 0xFFFFFFFF; the recovery branch then computes prescaler = 0xFFFFFFFF/0xFFFF + 1 = 65537 and underflows again. Verified by running the function's exact arithmetic: freq=84000001 → PSC=65537, ARR=4294967295. PSC is a 16-bit register so 65537 truncates to 1, and ARR truncates to 0xFFFF on TIM3/TIM4. init returns 0. For 42000000 < freq <= 84000000 it is not an underflow but still degenerate — ARR = 0, and every duty maps to CCR = 0. The tested values are fine (1 Hz → 1.000 Hz, 1 kHz → 1000.000 Hz, 100 kHz → 100000.000 Hz, all confirmed), which is exactly why the tests do not catch it.	Compute the divisor once and reject the degenerate range explicitly: if timer_clock / frequency_hz < 2, return -1. Then assert the achievable range in a test rather than leaving it implied.
9	Low	hal/src/hal_pwm.c:100, :133, :139, :266-272	ARPE (:100) and OCxPE (:133/:139) enable the ARR and CCR preload registers, but no update event is generated before the counter starts. The shadow registers therefore still hold their reset values for the first PWM period after eos_pwm_start(), so the first period runs at the reset ARR and duty.	Write tim->EGR = 1 (UG) after programming PSC/ARR/CCRx in init and in set_freq, before returning.
10	Low	hal/src/hal_pwm.c:124, :152	tim->RCR = 0 and tim->BDTR = TIM_BDTR_MOE write to offsets 0x30 and 0x44, which are reserved on TIM2–TIM5 — RCR and BDTR exist only on the advanced-control timers (TIM1/TIM8). The comment at :151 says "for advanced timers", which these are not, so the write is a knowing no-op into reserved space. The struct's offsets are otherwise correct (it mirrors the TIM1 layout, so CCR1–CCR4 land where they should), and I checked the CCMR1/CCMR2 shift arithmetic at :129-141 — 0x60 << shift does select PWM mode 1 for all four channels.	Delete both writes and the two macros behind them, or mark the two struct fields reserved0/reserved1 so the layout still documents itself.
11	Low	hal/src/hal_pwm.c:10, :316-324	The file header says the Linux backend is a "Software PWM simulation using timerfd". There is no timerfd anywhere in the file; the host backend generates no waveform at all — it records four values. sleep_ms (:321/:324) is defined and never called, and <time.h>, <stdlib.h>, <windows.h> and <unistd.h> (:316-323) are all unused. Pulling <windows.h> into a HAL translation unit for an unreferenced macro is a real cost on MSVC builds, which #132 is currently working to keep portable.	Reword the comment to say what the host backend is — a state-recording stub, not a simulation — and delete sleep_ms and the four includes. The PR body's "Cross-Platform Host Backend: Windows/Linux/macOS compatible simulation" should be corrected the same way.
12	Low	tests/test_pwm.c:251-268	test_pwm_stop_when_not_running asserts nothing: it captures the return value and discards it with (void)result at :265, commenting that the behaviour is "implementation-dependent". .ai/reviewer.md names "a verification whose result is discarded" as a finding. It is counted in the advertised 25. Separately, the suite has no per-test reset, so test_pwm_set_duty_not_initialized (:216) passes only because the preceding case happened to call eos_pwm_deinit(0).	Decide what stop() on a stopped channel returns, assert it, and document it in the header — the behaviour of this API is the thing the test exists to pin down. Add a setup() that clears channel state, as eBoot's suites do.
13	Low	hal/src/hal_pwm.c:389, tests/test_pwm.c:421	Both new files end without a trailing newline (\ No newline at end of file in the diff), and most lines in hal_pwm.c carry trailing whitespace.	Add the newlines and strip trailing whitespace.
14	Low	hal/src/hal_pwm.c:21, :67	REG32 and RCC_APB1ENR_REG are now defined a second time — hal/src/hal_extended.c:16 and :210 already define both, with the same values. §7.1 is explicit that architecture and SoC logic "must not be copied independently".	Move REG32 and the RCC/APB1 definitions into one SoC header included by both. This is the smaller half of the placement problem below.

Architecture conformance

Deviates, on placement; conforms on dependency direction.

• §5.1 architectural law — holds. hal_pwm.c includes only <eos/hal_extended.h> and <string.h>; nothing points up a tier, no product repo is referenced, and the new CMake entry adds hal/src/hal_pwm.c to eos_hal, which is the bottom library. No manifest changes.
• §21 tier placement — Tier 1 Foundation, eos. Correct repo. §21.1's split policy is not engaged; nothing wants its own repository.
• §5 "Hardware Platform" lists SoC support, BSP, HAL and Drivers as four distinct things, and .ai/architect.md is explicit that "hal/ contains no board specifics — those live in boards/" and "a board file is the leaf, never the trunk". This file puts STM32F4 SoC register addresses (TIM2_BASE–TIM5_BASE, :25-28), the RCC APB1 enable register (:67), and a hard-coded uint32_t timer_clock = 84000000 (:113, :229) directly in hal/src/. The 84 MHz figure is not even an SoC constant — it is an APB1 frequency that follows from the board's clock tree and PLL configuration, and eos/boards/stm32f407_discovery/ is where that belongs. §7.1: "Architecture and SoC logic must not be copied independently into every board."
  I am not treating this as the headline finding, because the repo already does it: hal/src/hal_extended.c and hal/src/hal_rtos.c both hold STM32F4 register code behind the same guard, and this PR follows that precedent rather than inventing it. But the precedent is what produced finding 14, and it is why an 84 MHz literal can be wrong for a board with no way for the board to say so. I have appended an architecture proposal about the design's silence here rather than asking this PR to relocate the file.
• §28 status and claims policy — not satisfied, and this is the substantive architectural objection. §28 requires, for Experimental, "Code, tests and documented limitations". The STM32F4 half has code, no tests (finding 4), and no documented limitations. The host half has code and tests, but the tests exercise argument validation and a boolean flag — nothing that could distinguish a working PWM from a stub. Moving the row off Planned is therefore ahead of the evidence for STM32F4 and arguably vacuous for the host. §28's opening rule — "Do not represent proposed or planned capabilities as implemented until the evidence model in this document is satisfied" — is the one this PR crosses.
• §22 hardware support tiers — untouched by the PR, and it should be: STATUS.md already records boards as Planned with "none has been validated on hardware". A PWM implementation with no board validation cannot lift that, and the PR does not claim it does. Correct restraint.

Proposed changes

Smallest sequence that keeps things working, in order:

1. hal/src/hal_pwm.c:85 — pwm_state[4] → pwm_state[16]. This is finding 1 and it is a one-token change; it should not wait on anything else.
2. hal/src/hal_pwm.c:92 — widen the guard to reject the two unvalidated parameters:

   if (!cfg || cfg->channel >= 16 || cfg->frequency_hz == 0 ||
       cfg->duty_pct_x10 > 1000) return -1;

   That closes findings 2 and 7 together.
3. hal/src/hal_pwm.c:115 — compute the divisor once and refuse the degenerate range (finding 8):

   uint32_t ticks = timer_clock / cfg->frequency_hz;
   if (ticks < 2) return -1;          /* frequency too high for this timer clock */
   uint32_t prescaler = (ticks + 0xFFFFu - 1) / 0xFFFFu;
   uint32_t period    = ticks / prescaler - 1;

   Apply the same three lines in eos_pwm_set_freq() at :227-233, which duplicates the arithmetic today.
4. Extend tests/test_pwm.c so 1–3 are actually pinned: a case that initialises every channel 0–15 and reads back through the API, and cases asserting -1 for frequency_hz = 0, duty_pct_x10 = 1001 and frequency_hz = 100000000. On the host backend the first of these already passes, so it does not protect finding 1 — which is the point of item 6 below.
5. Drop the six pwm_* pointers from hal/include/eos/hal_extended.h (finding 5), leaving that file untouched by this PR, unless the dispatch is wired in the same change.
6. Say plainly in the PR body and in STATUS.md:38 that the STM32F4 path is not compiled by any build target and therefore not covered by the 25 tests, and delete the ADC sentence (findings 3 and 4). Keeping the row at Planned for STM32F4 with a note that a host stub and its tests now exist would be the honest reading of §28; splitting the row into "HAL — extended peripherals (host)" and "(STM32F4)" would be better still, since the two have completely different evidence.
7. Findings 6, 9, 10, 11, 12, 13, 14 in the same pass — each is a few lines and none changes an interface.

I did not open a fix PR for finding 1, for two reasons: hal/src/hal_pwm.c does not exist on origin/master, so the fix-PR pipeline (which branches from the default branch) cannot express it; and the correct fix here belongs in the author's branch alongside items 2–4, not as a competing change.

Verification I ran

Detached worktree at the PR head, host GCC 13.

• Host build and tests, as claimed: cmake -B build -DEOS_BUILD_TESTS=ON && cmake --build build → rc 0, no PWM-related warnings. ./build/tests/test_pwm → 25/25 tests passed. ctest --test-dir build → 39/39 passed, 0 failed. The PR's host claims are accurate and nothing else regresses.
• Finding 1, dynamically: I copied hal_pwm.c, redirected TIM2_BASE–TIM5_BASE and RCC_APB1ENR_REG at a 1 KiB byte array so the STM32F4 branch could run on the host, compiled it with -fsanitize=address -DEOS_MCU_STM32F4 -DEOS_ENABLE_PWM=1 and called eos_pwm_init() with channel = 4:

  ERROR: AddressSanitizer: global-buffer-overflow
  WRITE of size 1 at 0x… thread T0
      #0 … in eos_pwm_init hal_pwm_repro.c:156
  0x… is located 0 bytes after global variable 'pwm_state' … of size 48
  

  48 bytes is 4 × 12, confirming the array is 4 entries. Only the base-address macros were changed; the indexing, the bounds check and the state writes are the PR's own code.
• Finding 2: same harness under -fsanitize=undefined -fno-sanitize-recover=all, frequency_hz = 0 → runtime error: division by zero at the timer_clock / cfg->frequency_hz line.
• Findings 7 and 8: ran the function's exact prescaler/period expression over {1, 1000, 100000, 84000001} Hz. The first three land on the requested frequency to three decimals; 84000001 yields PSC = 65537, ARR = 4294967295. eos_pwm_init() with duty_pct_x10 = 65535 returns 0.
• Finding 4: grep -rn EOS_MCU_STM32F4 cmake/ CMakeLists.txt → no match; the only definition is set(EOS_MCU_STM32F4 ON CACHE BOOL "") at toolchains/arm-cortex-m4.cmake:29, a CMake variable that never becomes -D. The ARM CI job's for src in … list (.github/workflows/build.yml:93-102) names 12 files; hal/src/hal_pwm.c is not among them, and neither is hal/src/hal_extended.c.
• Finding 5: grep -rn "s_ext_backend\|eos_hal_get_ext_backend" returns 5 hits, all setter/getter/declaration; grep -rn -- "->pwm_" returns nothing.
• Finding 3: ctest --test-dir build -N lists 39 tests; filtering for adc returns nothing, and ls tests/ | grep -i adc is empty.
• Compiler silence: gcc -std=c11 -Wall -Wextra -Warray-bounds=2 -O2 -DEOS_MCU_STM32F4 -DEOS_ENABLE_PWM=1 -c hal/src/hal_pwm.c → 0 warnings, rc 0. The STM32F4 branch compiles clean; every finding above survives -Wall -Wextra. Worth knowing before relying on the ARM job to catch this once the file is wired in.
• hal/src/hal_extended.c contains no PWM implementation, so there is no duplicate-symbol collision with the new file. Confirmed by grep.

Not checked

• CI. checks.txt is empty and gh pr checks 136 reports no checks on the branch. Every build and test result above is mine, not CI's.
• The STM32F4 register programming, on hardware or in emulation. No board, no QEMU run of this code, no logic-analyser capture. I verified the CCMR1/CCMR2 mode bits, the CCER enable shifts and the struct offsets by reading them against the TIM1/TIM2 layout, and I flagged what I found (findings 9, 10) — but that is inference from a datasheet layout, not a measurement. Whether this produces a correct waveform on an STM32F407 is Unknown, and after finding 4 nothing in the repo can currently tell you.
• Windows and macOS. The PR says "Verified on Windows host build"; I verified Linux only. <windows.h> and the _WIN32 branch at :319-321 were not compiled by me. #132 is concurrently working on MSVC portability and may interact with the new includes.
• The other 15 channels' timer mapping. channel_to_timer[]/channel_to_tim_ch[] (:87-88) map 16 channels onto TIM2–TIM5 × 4, which is arithmetically consistent, but I did not check that those 16 timer channels are actually routed to pins on any board in boards/, or that the pinmux for them exists. No GPIO alternate-function configuration appears anywhere in this PR, so on real hardware the timer would run with its output not connected to a pin — I did not confirm whether some other layer is expected to do that, and the PR does not say.
• products/vbox_test.h. I checked that the new EOS_ENABLE_PWM 1 line sits with the other feature macros, but did not build any product profile.
• Whether EOS_ENABLE_PWM reaches every translation unit consistently. Adding it to the EOS_BUILD_TESTS block in CMakeLists.txt:49-58 follows that block's stated rule ("this list is exactly the set the suite in tests/ covers") and is the right place. I did not audit the product-profile builds for translation units that see the macro differently, which is the ABI hazard in finding 5.

---

Automated architecture review of 96d9f6d2ba6b — scheduled, model claude-opus-5, checked against the EmbeddedOS Master Design v2.0. Advisory only: this reviewer never approves, requests changes, or merges. Reply here to discuss or push back — a wrong finding is a bug worth reporting.

[srpatcha]

Review — eos#136 "feat(hal): implement PWM peripheral with dual-platform support"

head: 538f35b author: NAVEENKUMARKR777 ci: none (no checks recorded on this head)

Verdict: The host half is honest and works — I built it and test_pwm reports 28/28, the whole ctest suite is 39/39 green, and the STATUS.md row is unusually candid about what is and is not real. The STM32F4 half is not: three register-level defects survive because nothing in the repository compiles or executes that code, and the PR body still describes it as production-ready.

Findings

#	Severity	File:line	Finding	Recommended fix
1	High	hal/src/hal_pwm.c:290-306	eos_pwm_stop() clears only CR1.CEN, and only when no other channel on the same timer is running. It never clears this channel's CCER.CCxE. On a timer with two active channels, stopping one leaves its output enabled and the timer running, so the pin keeps generating the waveform while the API returns 0 and pwm_state[ch].running reads false. Reproduced against a memory-mapped simulation of TIM2: init ch0 (1 kHz) and ch1 (2 kHz), start both, eos_pwm_stop(0) → 0, and afterwards CR1.CEN=1, CCER=0x011, CC1E still set. For a peripheral whose stated purpose in the PR body is motor and servo control, "stop" that does not stop is the wrong failure to ship. eos_pwm_deinit() at :193 already does this correctly.	Clear the channel output first, then decide about the timer: tim->CCER &= ~(TIM_CCER_CC1E << (tim_ch * 4)); before the timer_has_active_channel check at :300.
2	High	hal/src/hal_pwm.c:137, :229-285	Channels 1-4 of a timer share PSC/ARR, but eos_pwm_init() and eos_pwm_set_freq() write them as if the channel owned the timer, and never reconcile the siblings' recorded state. Two verified consequences on TIM2: (a) eos_pwm_init(ch1 @ 2 kHz) after eos_pwm_start(ch0 @ 1 kHz) executes tim->CR1 = TIM_CR1_ARPE — a plain assignment that clears CEN — so ch0's output stops while pwm_state[0].running stays true, and PSC goes 1→0 so ch0's frequency silently doubles to 2 kHz; (b) eos_pwm_set_freq(1, 500) afterwards moves PSC/ARR to 2/55999 and rescales only ch1's CCR, leaving CCR1 at 20999 — ch0's duty silently drifts from 50% to 37.5% and its frequency to 500 Hz, while pwm_state[0].frequency_hz still reports the original value. Nothing reports an error. Silent corruption of a running channel's output is worse than a rejection.	Make the shared resource explicit. Smallest correct version: track a per-timer frequency_hz set by the first init on that timer; have eos_pwm_init()/eos_pwm_set_freq() return -1 when another initialized channel on the same timer already holds a different frequency, and use tim->CR1 |= TIM_CR1_ARPE at :137 so an already-running timer is not stopped. If per-channel frequencies are wanted later, that needs a channel→timer allocator, not a fix here.
3	Medium	hal/src/hal_pwm.c:57, :153	#define TIM_CCMR2_OC3PE (1U << 11) names the wrong bit. In STM32F4 TIMx_CCMR2 (TIM2-TIM5) bit 3 is OC3PE and bit 11 is OC4PE — the register repeats the CCMR1 layout every 8 bits. With the << shift pattern at :153 this means TIM channel 3 sets OC4PE instead of OC3PE, and TIM channel 4 sets bit 19 — a reserved bit, outside the ~(0xFFU << shift) mask at :152, so it is never cleared — instead of OC4PE. Verified against a simulation: after eos_pwm_init(channel 2), CCMR2 = 0x00000860 (bit 3 = 0, bit 11 = 1); after eos_pwm_init(channel 3), CCMR2 = 0x00086000 (bit 11 = 0, bit 19 = 1). The OCxM = 110 mode bits are correct in both cases; only the preload bit is wrong. Without CCR preload, a duty change lands mid-period and can produce a truncated or missed pulse.	The layout repeats, so one constant covers both registers. Delete TIM_CCMR2_OC3PE and use TIM_CCMR1_OC1PE (bit 3) in both branches: tim->CCMR2 |= (0x60U << shift) | (TIM_CCMR1_OC1PE << shift);. Rename it TIM_CCMR_OCxPE if the CCMR1-specific name reads wrong.
4	Medium	PR body	The body does not describe this head. It claims "25 unit tests (25/25)" (the head has 28), "hal/src/hal_pwm.c (NEW - 383 lines)" (380), "tests/test_pwm.c (NEW - 421 lines)" (515), and "Added PWM to extended HAL backend registration system" — the only change to hal/include/eos/hal_extended.h is a one-line comment on an existing prototype; no registration system is touched. It also calls the result a "production-ready foundation" and says "Cross-platform compatibility ensured" and "Verified on Windows host build", with no command output. The STM32F4 code that is listed as the first Key Feature is compiled by no build target in this repository — the PR's own STATUS.md edit says so, and I confirmed it. Master design §28 states plainly that design intent is not evidence, and .ai/reviewer.md treats an unsupported "verified" as the finding itself. The STATUS.md rows in this same PR are more accurate than the PR description of them.	Rewrite the body to match STATUS.md: host PWM is a state-recording stub with 28 passing tests; the STM32F4 path is written but uncompiled, unexecuted and unvalidated. Paste the actual ctest -R test_pwm output. Drop "production-ready" and "ensured".
5	Low	tests/test_pwm.c:512-514	tests_run = 28; is a hand-maintained literal assigned once at the end of main(), not a counter. It is the number quoted in STATUS.md and in the PR body, so the headline evidence for this change rests on a constant a future edit can silently desynchronise from the run_*() call list directly above it.	Increment it where the test actually runs — add tests_run++; to the run_##name wrapper in the TEST macro at :23 and delete the literal. The tests_passed == tests_run return then means something.
6	Low	hal/src/hal_stm32f4_regs.h:8	The new header's block comment contains hal/src/*.c, and the /* inside it trips -Wcomment, which is part of -Wall. Verified: arm-none-eabi-gcc -mcpu=cortex-m4 -Wall -Wextra -c -DEOS_MCU_STM32F4 -DEOS_ENABLE_PWM=1 hal/src/hal_pwm.c emits warning: "/*" within comment [-Wcomment]. .github/workflows/build.yml:52 already builds one target with -Werror; the day this header reaches such a build it becomes a hard error.	Reword to "included only by C files under hal/src that need direct register access", or drop the glob.
7	Low	hal/src/hal_pwm.c:201 vs :340-341	The two backends disagree about eos_pwm_deinit(). The host version clears both initialized and running; the STM32F4 version clears only initialized and leaves running set. It is inert today because every entry point and timer_has_active_channel() gate on initialized, but the whole point of two backends behind one header is that the tests exercising one describe the other. The test suite only ever runs the host path, so this divergence is structurally invisible.	Add pwm_state[channel].running = false; at :201 so both backends leave the same state.

Architecture conformance

Deviates, but does not originate the deviation — worth recording rather than blocking on.

.ai/architect.md gives the reference layout for this repo and states it directly: hal/ is hardware abstraction and "contains no board specifics — those live in boards/", with dependencies pointing downward and inward. Master design §7.1 sets the hierarchy Architecture → SoC Family → SoC → Board and requires that "architecture and SoC logic must not be copied independently into every board", and §5 lists "SoC support", "BSP", "HAL" and "Drivers" as four distinct things under Hardware Platform.

hal/src/hal_pwm.c:36-53 puts TIM2-TIM5 base addresses, a full TIM_TypeDef register map, and a hard-coded #define TIMER_CLOCK_HZ 84000000UL APB1 assumption inside hal/. The new hal/src/hal_stm32f4_regs.h does the same for REG32 and RCC_APB1ENR. That is SoC-specific register code in the abstraction layer, and boards/stm32f407_discovery/ already exists as the place the layout designates.

This PR follows an established pattern rather than creating one: hal/src/hal_extended.c, hal/src/hal_rtos.c and the hal/src/hal_stm32f4/ directory are all already EOS_MCU_STM32F4-guarded SoC code under hal/, and extracting REG32/RCC_APB1ENR into a shared private header is a small step toward order, not away from it. So: no new cross-tier dependency, no import pointing up a tier, §5.1 intact. The layer boundary in .ai/architect.md is nonetheless not held here, and it will get harder to restore with each peripheral added this way. There is also a real gap in the master design behind this, which I have written up in .ai/autoreview/proposals/2026-09.md: the design names SoC support as a layer distinct from HAL and BSP, but neither the design nor the reference layout says which directory it lives in, so SoC register code has nowhere to go except hal/.

Tier placement is correct: PWM is a HAL peripheral in eos, Tier 1 — Foundation (§21). §21.1 is not engaged — nothing was split out. The hal_stm32f4_regs.h header is correctly kept out of hal/include/eos/, so the public contract other repos compile against did not widen.

Proposed changes

Smallest sequence that keeps every target building:

1. Findings 3 and 6 first — one constant and one comment, no behaviour change on any compiled target:

   -#define TIM_CCMR2_OC3PE   (1U << 11)
   ...
   -        tim->CCMR2 |= (0x60U << shift) | (TIM_CCMR2_OC3PE << shift);
   +        tim->CCMR2 |= (0x60U << shift) | (TIM_CCMR1_OC1PE << shift);

2. Finding 1 — one line added to eos_pwm_stop(), mirroring eos_pwm_deinit().
3. Finding 7 — one line added at :201.
4. Finding 2 — the real work. Add a static uint32_t timer_frequency_hz[4] alongside pwm_state, set it on the first init for a timer, reject a conflicting frequency from eos_pwm_init()/eos_pwm_set_freq(), and change :137 to |=. Do this on its own, not folded into 1-3.
5. Findings 4 and 5 — PR body and the tests_run counter.
6. Then close the gap that makes all of the above invisible: add hal/src/hal_pwm.c to the for src in … list in .github/workflows/build.yml:95-105 so the STM32F4 path is at least compiled with -Wall on every push. Compiling it is cheap and would have caught finding 6 immediately. Executing it needs QEMU or hardware and is a larger piece of work.

Verification I ran (not claims)

Fetched 538f35ba into a scratch clone; the local eos checkout was not modified.

• cmake -S . -B … -DEOS_BUILD_TESTS=ON && cmake --build … → exit 0. No new warning from hal_pwm.c or test_pwm.c in the host build.
• ctest -R test_pwm → Passed. ./tests/test_pwm prints 28/28 tests passed. ctest (full) → 39/39 passed. The host claim in STATUS.md holds.
• STATUS.md's numbers are accurate: hal/src/hal_extended_stubs.c is 707 lines and contains 268 (void)param;-form casts at this head.
• STATUS.md's "compiled by no build target" claim is accurate: .github/workflows/build.yml:95-105 cross-compiles an explicit source list that contains hal/src/hal_rtos.c and no other hal/src file — neither hal_pwm.c nor hal_extended.c. grep -rln EOS_MCU_STM32F4 hal/ boards/ drivers/ core/ returns exactly those three files.
• Cross-compiled the uncompiled path by hand: arm-none-eabi-gcc -mcpu=cortex-m4 -mthumb -std=c11 -Wall -Wextra -Os -c -DEOS_MCU_STM32F4 -DEOS_ENABLE_PWM=1 … hal/src/hal_pwm.c → compiles, with the -Wcomment warning of finding 6.
• Findings 1, 2 and 3 were each reproduced by compiling hal_pwm.c with the TIM/RCC base addresses redirected into a RAM buffer and driving the API from a host harness. The register values quoted in each finding are observed output from that run, not derived by reading.
• compute_prescaler_period() is sound across the range: 1 Hz → PSC 1281 / ARR 65522, 1 kHz → PSC 1 / ARR 41999, and ticks < 2 is rejected. No 16-bit overflow of ARR at any frequency I tried.

Not checked

• Nothing here has run on hardware or in an emulator, by me or by CI. Every STM32F4 finding above comes from a host simulation of the register file plus the STM32F4 reference-manual bit layout; I did not observe a real TIM2 peripheral, a real waveform, or a scope trace. STATUS.md's own "Never executed — no board, no QEMU" line applies to this review too.
• checks.txt is empty: no workflow of any kind ran on this head, so no lint, no cppcheck, no cross build result. The -Werror interaction in finding 6 is inferred from reading build.yml, not observed failing.
• I did not audit the remaining stubbed peripherals (ADC, I²C, SPI, CAN, DAC) in hal_extended_stubs.c — only the PWM block this diff removes.
• I did not verify that products/vbox_test.h's new EOS_ENABLE_PWM 1 is correct for whatever the vbox product is meant to be; it builds and tests clean, which is all I checked.
• The STM32F4 eos_pwm_init() never touches GPIO alternate-function or clock configuration for the output pin, so even with findings 1-3 fixed the pin would not toggle without board-level pinmux. I did not trace whether boards/stm32f407_discovery/board_stm32f407vg.c is expected to do that, and it is outside this diff.

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Automated architecture review of 538f35baf731 — scheduled, model claude-opus-5, checked against the EmbeddedOS Master Design v2.0. Advisory only: this reviewer never approves, requests changes, or merges. Reply here to discuss or push back — a wrong finding is a bug worth reporting.