feat: parallel incremental BVH + alternative sweep toi implementation

.github/workflows/parry-ci-build.yml

@@ -35,10 +35,8 @@ jobs:
         run: cargo build --verbose -p parry2d;
       - name: Build parry3d
         run: cargo build --verbose -p parry3d;
-      - name: Build parry2d SIMD
-        run: cd crates/parry2d; cargo build --verbose --features simd-stable;
-      - name: Build parry3d SIMD
-        run: cd crates/parry3d; cargo build --verbose --features simd-stable;
+      - name: Build parry3d 8-lanes SIMD
+        run: cd crates/parry3d; cargo build --verbose --features simd8;
       - name: Check serialization
         run: cargo check --features bytemuck-serialize,serde-serialize,rkyv;
       - name: Check enhanced-determinism

CHANGELOG.md

@@ -1,3 +1,33 @@
+## Unreleased
+
+### Breaking changes
+
+- The `simd-stable` and `simd-nightly` features were removed. 4-lane SIMD is now always enabled
+  (it falls back to scalar code on targets without SIMD support). The new opt-in `simd8` feature
+  widens SIMD to 8 lanes for `f32` builds; it requires an AVX-enabled target to actually emit
+  256-bit instructions, and is incompatible with `enhanced-determinism`.
+- `ContactManifold::subshape_pos1`/`subshape_pos2` are no longer public fields. They are replaced by
+  a single boxed `subshape_poses: Option<Box<SubshapePoses>>` field (to shrink `ContactManifold`),
+  accessed through the new `subshape_pos1()`/`subshape_pos2()` getters and
+  `set_subshape_pos1`/`set_subshape_pos2` setters.
+
+### Added
+
+- `query::sweep_toi`: sweep-based time-of-impact queries. A timestep is modeled as a `Sweep` between
+  two endpoint poses (linear translation + rotation nlerp), and `sweep_time_of_impact` (plus
+  `sweep_time_of_impact_composite` for composite shapes) computes the earliest time the swept shapes
+  reach a slop-based target separation, using conservative advancement. Also exports `ToiProxy`,
+  `SimplexCache`, `SweepToiOutput`, `SweepToiStatus`, and `SweepCompositeFastShape`.
+- `Bvh` gains incremental and parallel update APIs: `refit_partial`, flag-preserving
+  `refit_without_resolve` variants, `refit_parallel`, parallel BVTT traversal, and batched
+  parallel leaf updates (`insert_or_update_batch_partially_parallel`,
+  `reinsert_or_update_with_change_detection`, `reinsert_or_update_if_present`,
+  `update_partially_if_present`, and the `BvhLeafUpdateStatus` enum).
+
+### Modified
+
+- Cuboid support-face feature ids are now computed with bit operations instead of lookup tables.
+
 ## 0.29.0
 
 ### Breaking changes

Cargo.toml

@@ -41,7 +41,7 @@ downcast-rs = { version = "2", default-features = false, features = ["sync"] }
 num-traits = { version = "0.2", default-features = false }
 slab = "0.4"
 arrayvec = { version = "0.7", default-features = false }
-simba = { version = "0.10", default-features = false }
+simba = { version = "0.10.1", default-features = false }
 glamx = { version = "0.3", default-features = false, features = ["nostd-libm"] }
 approx = { version = "0.5", default-features = false }
 serde = { version = "1.0", features = ["derive"] }

crates/parry2d-f64/Cargo.toml

@@ -44,18 +44,15 @@ serde-serialize = [
 ]
 rkyv = ["dep:rkyv", "glamx/rkyv"]
 bytemuck-serialize = ["bytemuck", "glamx/bytemuck"]
-simd-stable = ["simba/wide", "simd-is-enabled"]
-simd-nightly = ["simba/portable_simd", "simd-is-enabled"]
-enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm"]
+# No-op for f64 (simba has no 8-lane f64 type); declared so the shared
+# `src/lib.rs` cfg resolves. f64 SIMD stays 4-lane.
+simd8 = []
+enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm", "glamx/scalar-math"]
 parallel = ["rayon"]
 alloc = ["hashbrown"]
 spade = ["dep:spade", "alloc"]
 improved_fixed_point_support = []
 
-# Do not enable this feature directly. It is automatically
-# enabled with the "simd-stable" or "simd-nightly" feature.
-simd-is-enabled = []
-
 [lib]
 name = "parry2d_f64"
 path = "../../src/lib.rs"
@@ -68,7 +65,7 @@ downcast-rs = { workspace = true }
 num-traits = { workspace = true }
 slab = { workspace = true, optional = true }
 arrayvec = { workspace = true }
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 glamx = { workspace = true, features = ["approx", "f64", "i64"] }
 approx = { workspace = true }
 serde = { workspace = true, optional = true }
@@ -88,7 +85,7 @@ smallvec = { workspace = true }
 foldhash = { workspace = true }
 
 [dev-dependencies]
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 oorandom = { workspace = true }
 ptree = { workspace = true }
 rand = { workspace = true }

crates/parry2d/Cargo.toml

@@ -44,19 +44,16 @@ serde-serialize = [
 ]
 rkyv = ["dep:rkyv", "glamx/rkyv"]
 bytemuck-serialize = ["bytemuck", "glamx/bytemuck"]
-simd-stable = ["simba/wide", "simd-is-enabled"]
-simd-nightly = ["simba/portable_simd", "simd-is-enabled"]
-enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm"]
+# Widens SIMD from 4 to 8 lanes (f32 only). Needs an AVX-enabled target to
+# emit 256-bit code.
+simd8 = []
+enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm", "glamx/scalar-math"]
 parallel = ["rayon"]
 alloc = ["hashbrown", "smallvec", "downcast-rs", "glamx/approx"]
 spade = ["dep:spade", "alloc"]
 improved_fixed_point_support = []
 encase = [ "dep:encase", "glamx/encase" ]
 
-# Do not enable this feature directly. It is automatically
-# enabled with the "simd-stable" or "simd-nightly" feature.
-simd-is-enabled = []
-
 [lib]
 name = "parry2d"
 path = "../../src/lib.rs"
@@ -69,7 +66,7 @@ downcast-rs = { workspace = true, optional = true }
 num-traits = { workspace = true }
 slab = { workspace = true, optional = true }
 arrayvec = { workspace = true }
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 glamx = { workspace = true, features = ["i32"] }
 approx = { workspace = true }
 serde = { workspace = true, optional = true }
@@ -90,7 +87,7 @@ foldhash = { workspace = true }
 encase = { workspace = true, optional = true }
 
 [dev-dependencies]
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 oorandom = { workspace = true }
 ptree = { workspace = true }
 rand = { workspace = true }

crates/parry3d-f64/Cargo.toml

@@ -42,8 +42,9 @@ serde-serialize = [
 ]
 rkyv = ["dep:rkyv", "glamx/rkyv"]
 bytemuck-serialize = ["bytemuck", "glamx/bytemuck"]
-simd-stable = ["simba/wide", "simd-is-enabled"]
-simd-nightly = ["simba/portable_simd", "simd-is-enabled"]
+# No-op for f64 (simba has no 8-lane f64 type); declared so the shared
+# `src/lib.rs` cfg resolves. f64 SIMD stays 4-lane.
+simd8 = []
 enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm", "glamx/scalar-math"]
 parallel = ["rayon"]
 # Adds `TriMesh:to_obj_file` function.
@@ -52,10 +53,6 @@ alloc = ["hashbrown"]
 spade = ["dep:spade", "alloc"]
 improved_fixed_point_support = []
 
-# Do not enable this feature directly. It is automatically
-# enabled with the "simd-stable" or "simd-nightly" feature.
-simd-is-enabled = []
-
 [lib]
 name = "parry3d_f64"
 path = "../../src/lib.rs"
@@ -68,7 +65,7 @@ downcast-rs = { workspace = true }
 num-traits = { workspace = true }
 slab = { workspace = true, optional = true }
 arrayvec = { workspace = true }
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 glamx = { workspace = true, features = ["approx", "f64", "i64"] }
 approx = { workspace = true }
 serde = { workspace = true, optional = true, features = ["rc"] }

crates/parry3d/Cargo.toml

@@ -43,8 +43,9 @@ serde-serialize = [
 rkyv = ["dep:rkyv", "glamx/rkyv"]
 bytemuck-serialize = ["bytemuck", "glamx/bytemuck"]
 
-simd-stable = ["simba/wide", "simd-is-enabled"]
-simd-nightly = ["simba/portable_simd", "simd-is-enabled"]
+# Widens SIMD from 4 to 8 lanes (f32 only). Needs an AVX-enabled target to
+# emit 256-bit code.
+simd8 = []
 enhanced-determinism = ["simba/libm_force", "indexmap", "glamx/libm", "glamx/scalar-math"]
 parallel = ["rayon"]
 # Adds `TriMesh:to_obj_file` function.
@@ -54,10 +55,6 @@ spade = ["dep:spade", "alloc"]
 improved_fixed_point_support = []
 encase = [ "dep:encase", "glamx/encase" ]
 
-# Do not enable this feature directly. It is automatically
-# enabled with the "simd-stable" or "simd-nightly" feature.
-simd-is-enabled = []
-
 [lib]
 name = "parry3d"
 path = "../../src/lib.rs"
@@ -70,7 +67,7 @@ downcast-rs = { workspace = true, optional = true }
 num-traits = { workspace = true }
 slab = { workspace = true, optional = true }
 arrayvec = { workspace = true }
-simba = { workspace = true }
+simba = { workspace = true, features = ["wide"] }
 glamx = { workspace = true, features = ["i32"] } # , "approx"] }
 approx = { workspace = true }
 serde = { workspace = true, optional = true, features = ["rc"] }

src/bounding_volume/mod.rs

@@ -3,7 +3,6 @@
 #[doc(inline)]
 pub use crate::bounding_volume::aabb::Aabb;
 
-// #[cfg(feature = "simd-is-enabled")]
 // pub use crate::bounding_volume::simd_aabb::SimdAabb;
 
 #[doc(inline)]
@@ -62,7 +61,6 @@ mod bounding_sphere_utils;
 #[cfg(feature = "alloc")]
 mod bounding_sphere_voxels;
 
-// #[cfg(feature = "simd-is-enabled")]
 // mod simd_aabb;
 
 /// Free functions for some special cases of bounding-volume computation.

src/lib.rs

@@ -23,29 +23,21 @@ the rust programming language.
 #![cfg_attr(feature = "dim3", doc(html_root_url = "https://docs.rs/parry3d"))]
 #![no_std]
 
-#[cfg(all(
-    feature = "simd-is-enabled",
-    not(feature = "simd-stable"),
-    not(feature = "simd-nightly")
-))]
-std::compile_error!("The `simd-is-enabled` feature should not be enabled explicitly. Please enable the `simd-stable` or the `simd-nightly` feature instead.");
-#[cfg(all(feature = "simd-is-enabled", feature = "enhanced-determinism"))]
-std::compile_error!(
-    "SIMD cannot be enabled when the `enhanced-determinism` feature is also enabled."
+#[cfg(all(feature = "simd8", feature = "enhanced-determinism"))]
+core::compile_error!(
+    "8-lanes SIMD cannot be enabled when the `enhanced-determinism` feature is also enabled because it breaks cross-platform determinism."
 );
 
-#[cfg(feature = "simd-is-enabled")]
 #[allow(unused_macros)]
 macro_rules! array(
     ($callback: expr; SIMD_WIDTH) => {
         {
             #[inline(always)]
             #[allow(dead_code)]
-            fn create_arr<T>(mut callback: impl FnMut(usize) -> T) -> [T; SIMD_WIDTH] {
-                #[cfg(not(feature = "simd-is-enabled"))]
-                return [callback(0usize)];
-                #[cfg(feature = "simd-is-enabled")]
-                return [callback(0usize), callback(1usize), callback(2usize), callback(3usize)];
+            fn create_arr<T>(callback: impl FnMut(usize) -> T) -> [T; SIMD_WIDTH] {
+                // Width-agnostic: `N` is inferred from the `[T; SIMD_WIDTH]` return type,
+                // so this covers the 1-, 4-, and 8-lane builds alike.
+                core::array::from_fn(callback)
             }
 
             create_arr($callback)
@@ -84,39 +76,36 @@ pub mod shape;
 pub mod transformation;
 pub mod utils;
 
-#[cfg(not(feature = "simd-is-enabled"))]
 mod simd {
-    /// The number of lanes of a SIMD number.
-    pub const SIMD_WIDTH: usize = 1;
-    /// SIMD_WIDTH - 1
-    pub const SIMD_LAST_INDEX: usize = 0;
-
-    /// A SIMD float with SIMD_WIDTH lanes.
-    #[cfg(feature = "f32")]
-    pub type SimdReal = f32;
-
-    /// A SIMD float with SIMD_WIDTH lanes.
-    #[cfg(feature = "f64")]
-    pub type SimdReal = f64;
-
-    /// A SIMD bool with SIMD_WIDTH lanes.
-    pub type SimdBool = bool;
-}
-
-#[cfg(feature = "simd-is-enabled")]
-mod simd {
-    #[cfg(all(feature = "simd-nightly", feature = "f32"))]
-    pub use simba::simd::{f32x4 as SimdReal, mask32x4 as SimdBool};
-    #[cfg(all(feature = "simd-stable", feature = "f32"))]
+    // The `wide` types fall back to scalar code on targets without SIMD, so
+    // they are always used, whatever the platform.
+
+    // 8-lane SIMD (f32 only; simba has no `WideF64x8`). Opt-in via `simd8`.
+    // Requires an AVX-enabled target (`RUSTFLAGS="-C target-feature=+avx2,+fma"`
+    // or `-C target-cpu=native`) for the compiler to actually emit 256-bit
+    // instructions; otherwise it runs (correctly) as two 128-bit halves.
+    #[cfg(all(feature = "simd8", feature = "f32"))]
+    pub use simba::simd::{WideBoolF32x8 as SimdBool, WideF32x8 as SimdReal};
+
+    // 4-lane SIMD (default width).
+    #[cfg(all(not(feature = "simd8"), feature = "f32"))]
     pub use simba::simd::{WideBoolF32x4 as SimdBool, WideF32x4 as SimdReal};
 
-    #[cfg(all(feature = "simd-nightly", feature = "f64"))]
-    pub use simba::simd::{f64x4 as SimdReal, mask64x4 as SimdBool};
-    #[cfg(all(feature = "simd-stable", feature = "f64"))]
+    // f64 stays 4-lane regardless of `simd8` (no 8-lane f64 type in simba).
+    #[cfg(feature = "f64")]
     pub use simba::simd::{WideBoolF64x4 as SimdBool, WideF64x4 as SimdReal};
 
     /// The number of lanes of a SIMD number.
+    #[cfg(all(feature = "simd8", feature = "f32"))]
+    pub const SIMD_WIDTH: usize = 8;
+    /// SIMD_WIDTH - 1
+    #[cfg(all(feature = "simd8", feature = "f32"))]
+    pub const SIMD_LAST_INDEX: usize = 7;
+
+    /// The number of lanes of a SIMD number.
+    #[cfg(not(all(feature = "simd8", feature = "f32")))]
     pub const SIMD_WIDTH: usize = 4;
     /// SIMD_WIDTH - 1
+    #[cfg(not(all(feature = "simd8", feature = "f32")))]
     pub const SIMD_LAST_INDEX: usize = 3;
 }

src/partitioning/bvh/bvh_binned_build.rs

@@ -27,6 +27,7 @@ impl Bvh {
 
         self.nodes.clear();
         self.parents.clear();
+        self.free_wide_nodes.clear();
         self.nodes.push(BvhNodeWide::zeros());
         self.parents.push(BvhNodeIndex::default());