Implement STM32F7 SAI2 transport with circular DMA

[JaxCalder]

Add the first hardware transport implementation for STM32F746G-DISCO: SAI2 A master TX and B synchronous RX, circular DMA2 with half/complete/error notifications, 16/24/32-bit samples, explicit buffer lifetime and stop/restart. Reserve DMA streams and the PLLI2S clock, reject foreign owners, and retain ownership if shutdown fails. The core and STM32F7 port are independently packaged modules linked through the Module API. Include board GPIO routing, API documentation, native contract tests, CI and a physical-board test application.

Depends on choco-technologies/dmclk#33 and dmclk >=1.2. CI temporarily builds headers from its pinned commit; release packaging requires that clock version to be published first.

Validation:

• Native production-core contract suite passes (invalid formats/buffers, overlap, failure propagation, lifecycle and event counters).
• STM32F7 core, port and physical-test modules build successfully; the core also compiles for the host.
• STM32F746G-DISCO: physical test passes. 48 kHz/16-bit TX: 99 complete events/s; 44.1 kHz/16-bit TX/RX: 91/91; 48 kHz/24-bit and 32-bit TX/RX: 99/99. No DMA/FIFO errors; stop/restart and exclusive ownership pass.
• Physical testing exposed the DMA channel-zero/NONE collision. SAI2_B now supplies nonzero request alias8, mapped by the existing STM32 dmdma port to CHSEL0, preserving its ABI.
• Test used a clean dmod-boot build with a minimal dmclk/dmdma configuration and local modules. Its generated config image was aligned to four bytes; full-system boot problems before the test were excluded. Firmware/modules from before testing are backed up and restored separately.

This transport does not initialize WM8994 or expose /dev/audio. It currently accepts only the STM32F746 non-cacheable DTCM DMA heap; cached SRAM/SDRAM need an explicit cache-maintenance contract. Acoustic playback and valid microphone samples require the subsequent codec driver.