Mux the STM32F746G-DISCO SDRAM pins one GPIO port at a time

[JohnAmadis]

Problem

configs/board/stm32f746g-disco/sdram.ini configured each of the 40 SDRAM pins in its own dmgpio section. All 40 sections had exactly the same settings: AF12, mode=alternate, speed=maximum, output_circuit=push_pull, driver_order=-9.

Every section becomes a separate driver node that dmdevfs configures on its own, which costs ~4 ms per pin on dmod-boot.

Change

The pins are now grouped into one section per GPIO port: sdram_port_c … sdram_port_i, 7 sections in total. Each section selects its pins with a pins= bitmask, the same way dmlcdtft's lcd.ini configures the LCD pins.

Port	pins	Signals
C	0x0008	SDCKE0
D	0xC703	D0–D3, D13–D15
E	0xFF83	NBL0, NBL1, D4–D12
F	0xF83F	A0–A9, SDNRAS
G	0x8133	A10, A11, BA0, BA1, SDCLK, SDNCAS
H	0x0028	SDNE0, SDNWE
I	0x0030	NBL2, NBL3

• The signal name of every pin is kept in a comment above its port section.
• The header notes are kept, including the one about D16–D31 not being wired.
• The set of pins is unchanged: a script checked it against the old file (40 = 40).
• The [sdram] section is byte-identical.

Measured on dmod-boot (Renode, STM32F746G-DISCO, virtual time)

Measured with this exact sdram.ini in dmod-boot's config filesystem; everything else unchanged.

	Before	After
Nodes configured by dmdevfs	85	52
SDRAM (dmfmc) configured	631 ms	332 ms
/dev mounted	1292 ms	957 ms
Splash on the LCD (first frame)	1223 ms	895 ms
Shell prompt	1558 ms	1238 ms

• The SDRAM comes up the same way: FMC: SDRAM bank 1 configured at 72000000 Hz (CAS=2, width=2 bytes), and the SDRAM heap is registered (8 MiB).
• The splash frame, whose framebuffer lives in SDRAM, is byte-identical to the one before the change.
• The boot log has the same warnings and errors.

Together with choco-technologies/dmlcdtft#6 (display configured right after the SDRAM), the splash should come up at about 0.4 s. I did not measure that combination.

🤖 Generated with Claude Code

https://claude.ai/code/session_01V9XGvT9zLJVAagoEVhYh9T

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