arch/tricore: drop iLLD dependency in cache and perf paths - #19783
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zyfeier wants to merge 3 commits into
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arch/tricore: drop iLLD dependency in cache and perf paths#19783zyfeier wants to merge 3 commits into
zyfeier wants to merge 3 commits into
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Add tricore_mtcr()/tricore_mfcr() inline-assembly wrappers for the MTCR/MFCR (move to/from Core Special Function Register) instructions. These let arch/tricore code access CSRs directly without relying on the Infineon iLLD intrinsics, and are used by the following iLLD-removal change in the performance-counter path. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Replace the iLLD register structures (Ifx_CPU_PCON0/1/2, Ifx_CPU_DCON0/1/2) and the IfxCpu_cfg.h cache-size/line-size macros in the cache path with direct CSR accesses via tricore_mtcr()/tricore_mfcr() and locally defined PCON/DCON bit masks. Also switch __isync()/__dsync() to the UP_ISB()/ UP_DSB() barrier wrappers. This removes the arch/tricore cache path's dependency on the Infineon iLLD layer. No behavior change. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
Replace the iLLD helpers IfxCpu_resetAndStartCounters() and IfxCpu_getClockCounter() in the performance-counter path with direct CSR accesses via tricore_mtcr()/tricore_mfcr(). tricore_reset_ccnt() disables the CPU cycle counter (CPU_CCTRL), clears CPU_CCNT, then re-enables it; up_perf_gettime() reads CPU_CCNT directly. This removes the arch/tricore perf path's dependency on the Infineon iLLD layer. No behavior change. Signed-off-by: zhangyu117 <zhangyu117@xiaomi.com>
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Aug 11, 2026
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Summary
Remove the Infineon iLLD dependency from the arch/tricore cache and
performance-counter paths, replacing the iLLD intrinsics and register
structures with direct CSR (Core Special Function Register) accesses.
The series contains three commits, kept separate to match the internal
development history:
tricore_mtcr()/tricore_mfcr()inline-assembly wrappers for theMTCR/MFCR instructions in
arch/arch.h, so arch/tricore code can accessCSRs without the iLLD intrinsics.
(
Ifx_CPU_PCON0/1/2,Ifx_CPU_DCON0/1/2) andIfxCpu_cfg.hcache macrosin
tricore_cache.cwithtricore_mtcr()/tricore_mfcr()plus locallydefined PCON/DCON CSR numbers and bit masks.
barriers.hUP_ISB()/UP_DSB()now emit theisync/dsyncinstructions directly instead ofthe iLLD
__isync()/__dsync()intrinsics.IfxCpu_resetAndStartCounters()and
IfxCpu_getClockCounter()with direct CCTRL/CCNT CSR accesses.The CSR register numbers previously pulled in from the iLLD
IfxCpu_reg.hare now defined locally in each file that needs them.
Impact
Testing
Build (0 errors, ELF produced):
Runtime (flashed to TC4x board, boots to NSH):